The PC-ATOMIC card is a i486 VL-bus host interface capable of interfacing to the Myrinet at the physical link layer. It provides a bidirectional 640 Mbps (80 MBps, byte-wide) channel over Myricom links, and is link-compatible with Myricom’s Sun SPARC SBus interface.
For more information, see:
- PC-ATOMIC README Text-only description of the project.
- Summary report Full final report of the project.
Small quantities of the board are available now as GFE for research purposes.
Contact Joe Touch for more information.
Board diagram
Board photo
Host requirements
- VL-bus at 33 Mhz
- 1-wait state memory (or faster)
- i486 processor
- fits a short-form VL-bus slot
Software support
C-code interface library and headers are provided.
Sample files compatible with NetBSD 0.9 are also provided.
Use of the boards requires Myricom’s LANai compiler and information on the LANai 1.2 interface processor. USC/ISI does not distribute code related directly to the Myricom LANai processor, including the cclan compiler, lanai.h include files (defining LANai registers), and LANai specifications. Contact Myricom for information regarding these items.
Interface board capabilities
- A graph of performance measurements
- IP checksum during programmed I/O
- J. Touch, B. Parham, “Implementing the Internet Checksum in Hardware” RFC-1936, ISI, April, 1996.
- The implementation is based on a pair of 16-bit toroidally-pipelined adders. The adders (shown below) are composed of 2- and 3-bit fast carry-lookahead components, with carries pipelined between components. The adder inputs one data word per input clock, and requires 6 additional clocks of idle input to propagate the carries through the pipeline.
- Maskable on-board processor interrupts
- Available DMA counters
- DMA support may be available in a future firmware release.
- A variety of board flows are possible
Idle: 
DMA Read: 
DMA Write: 
Host Read Memory: 
Host Write Memory: 
Host Read Register: 
Host Write Register: 
Lanai Read Register: 
Lanai Write Register: 