The Internet Checksum in Hardware The Internet Checksum in Hardware
RFC 1936 describes how to compute the Internet checksum in a $40 PLD at 1.2 Gbps (32 bits wide, 25 ns per word).
The RFC is available on-line (also as text):
The implementation is based on a pair of 16-bit toroidally-pipelined adders. The adders (shown below) are composed of 2- and 3-bit fast carry-lookahead components, with carries pipelined between components. The adder inputs one data word per input clock, and requires 6 additional clocks of idle input to propagate the carries through the pipeline.
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This page written and maintained by Joe Touch touch@isi.edu
Last modified June 2, 1997.