Gopi Neela and Jeffrey Draper. An Asymmetric Adaptive-Precision Energy-Efficient 3DIC Multiplier. Great Lakes Symposium on VLSI (GLSVLSI), 2013.
Gopi Neela and Jeffrey Draper. Logic-on-Logic Partitioning Techniques for 3-Dimensional Integrated Circuits. The IEEE International Symposium on Circuits and Systems (ISCAS), 2013.
Gopi Neela and Jeffrey Draper. Challenges in 3DIC implementation of a design using current CAD tools. The IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012.
Himanshu Thapliyal, Gopi Neela, Kumar KKP, and Srinivas MB. Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. The IEEE Conference on Computer Systems and Applications, 2006.