Paper:#1/5/2003

ISSN 1213-161X

Content

MOSFET Device Modeling Using Methods of Asymptotic Analysis

Henok Abebe and Vance Tyree

Information Sciences Institute,

4676 Admiralty Way, Marina del Rey, California 90292-6695 USA

Ellis Cumberbatch

Department of Mathematics, Claremont Graduate University,

121 E. Tenth Street, Claremont, CA 91711, USA.

Hedley Morris

Department of Mathematics, San Jose State University,

One Washington Square, San Jose, CA 95192, USA.

Abstract:Methods of asymptotic analysis are used to develop a physical quasi-one-dimensional MOSFET model with fewer model parameters. Discontinuities at the boundaries between regimes are avoided by using a hyperbolic blending function. A smooth function over two different regimes leads to a good conductance model. Using a single set of model parameters gives good comparisons with measured data and there is also improvement in modeling the saturated current compared with commonly used MOSFET models.

INTRODUCTION

The silicon-based metal-oxide-semiconductor field effect transistor (MOSFET) is currently the dominant technology for designing very-large-scale integrated (VLSI) circuits. The first silicon based MOSFET devices were fabricated in 1960, and since then they have replaced the vacuum tube in almost all-electronic applications. One of the deficiencies of many MOSFET models is that they are regional and can have discontinuities at the boundaries between regimes. This causes problems for the derivative terms (the conductances). Circuit simulation would be significantly improved if the I-V models could be made into single-piece smooth function. Also, they should have simple form for extracting the model parameters. The discontinuity problem is handled in most current SPICE models using an exponential smoothing function.

A recent paper [1] uses another approach and describes a single I-V model equation across different operational regimes of the MOSFET using a hyperbolic blending function. In [1], the asymptotic analysis presented in [3] was improved to achieve explicit I-V formula in various regimes, and the formulae successfully "blended" across regime boundaries. The formulae then compared with the numerical [2] and asymptotic [3] results.

In this paper we simplify the equations in [1] and derive the I-V equations as a function of the threshold voltage, which is an important parameter in circuit design and simulation. Our final equations simplify parameter extraction and also extend the model further in the sub-threshold region. The results in Figure 1 to 4 are from a single set of model parameters that are listed in Table I and show good comparison with measured data. All these are significant improvements over [1].

LINEAR REGIME

The following parameter scaling is used in [1] for the gate voltage, drain voltage, gate oxide capacitance, surface potential, and quasi-Fermi potential parameters respectively.

(1)

Parameter N is the channel doping density. e_i , permittivity of the insulator. t_ox , thickness of the insulator. e_s , semiconductor permittivity. K_b , Boltzmann constant. T, temperature. V_fb , flat band voltage. x₁ , co-ordinate perpendicular to the MOSFET channel. qis the electron charge, and n_i is the intrinsic carrier density.

(2)

The current along the channel is derived as a function of the carrier effective mobility m_eff , effective device width W_eff , and length L_eff as found in [1, Equation (45); 3, Equation (3.6)]

(3)

The current along the channel can be simplified using (2)

(4)

(5)

The parameter V_T is the threshold voltage and its first order approximation is given by,

(6)

This can be related to the classical threshold voltage model of MOS device without the short channel effects, defined as a function of the substrate bias voltage V_bs

(7)

The threshold voltage usually written in the following form,

(8)

Modeling I-V characteristics of the transistor as functions of the threshold voltage is very useful for circuit designers. It gives designers the value of the gate voltage at which the transistor will be turned on. When the gate voltage reaches the threshold voltage, the substrate underneath the gate becomes inverted.

The model derived in this section, Equation (5), is exactly same as the classic MOS square law model for device operating in the linear regime. However, our asymptotic calculation gives additional terms in the saturation regime and improves the saturation model.

SATURATION REGION

In this regime the current along the channel no longer increases with increasing drain bias for long channel devices. When the drain voltage reaches saturation (V_ds = V_dsat ), the channel pinches off and the inversion layer no longer reaches the drain. When V_ds > V_dsat , the pinch-off point moves away from the drain junction and toward the source. This means the effective channel length will decrease in the saturation regime (L_eff > L_sat ). Since the inversion layer no longer reaches the drain, determining the potential at pinch-off is very critical in finding the saturated current. Ward [3] gives a criterion for pinch-off [3, see bottom of p. 1120]

(9)

Also using

and solving (9) for the Fermi-potential gives [1, Equation (33)]:

(10)

Integrating (4) from zero to f_p gives the saturated current and solving (9) for the Fermi-potential gives [1, Equation (33)]:

(11)

(16)

There are other mechanisms that affect the saturated current and the threshold voltage of small devices (L < 0.9 micrometer). Substrate current induced body effect (SCBE) is usually caused by impact ionization, where hot carriers collide with the silicon atoms and generate electron-hole pairs. The holes into the bulk appear as substrate current. This will increase the drain current and reduce the threshold voltage. Threshold voltage reduction also occurs due to drain-induced barrier lowering (DIBL). If the channel is very short, the applied drain bias affects the channel potential. It lowers the gate bias and this will decrease the threshold voltage. There is also a strong dependence of the threshold voltage on the channel length, width, substrate doping, and the drain voltage [5].

Therefore modeling the remaining short channel effects requires further study in the areas of threshold voltage and impact ionization.

BLENDING

The following functions are used to blend solutions of two different regimes, [1]:

(17)

The above blending functions are essentially unity in one regime and zero in the other and they give a smooth transition across x = a. For example F^- (a,x,b) is unity in x < a and zero in x > a, on the other hand F⁺ (a,x,b) is unity in x > a and zero in the complement. Hence our solutions for the current can be written,

(18)

(19)

The channel conductances g_ds and g_m , from derivatives of (18) and (19), can be achieved without discontinuities. The measured data used for the following comparisons are from 0.25micron technology with channel doping density 2.4 X 10¹⁷cm ^{- 3}, and oxide thickness 5.6 nm. The comparisons below are done from NMOS device with channel length 0.96, and width 20 micrometer.

(a)

(b)

Fig. 1 (a) Channel current as a function of gate voltage with substrate bias voltages: 0V, -0.5V, -1V, -1.5V, -2V, and –2.5V from left to right. Blending the sub-threshold and linear regimes is achieved without discontinuities. L=0.96 micrometer, and W=20 micrometer (b) Channel current in log scale as a function of gate voltage.

Fig. 2 Channel current as a function of drain voltage with gate voltages: 1.02V, 1.316V, 1.612V, 1.908V, 2.204V, and 2.5V from bottom to top. Blending the linear and saturated regimes is achieved without discontinuities. L=0.96 micrometer, and W=20 micrometer.

Fig. 3 Derivative of the current in Fig. 1 versus gate voltage

Fig. 4 Derivative of the current in Fig. 2 versus drain voltage