Ultra Lightweight Runtime Kernels for PIM-enabled Petaflops-scale Architectures
Thomas Sterling, California Institute of Technology
Abstract
The emergence of Processor-in-Memory (PIM) hardware structures as an enabling means for computing in the trans-Petaflops performance regime either in conjunction with complementing very high speed numeric processors or in standalone PIM arrays (i.e. "Sea of PIMs") requires an innovation in software support for operating systems and runtime services. PIM differs from conventional systems in that its full functionality is derived from the cooperative operation of many small computing elements, none of which alone, would be capable of providing the necessary capability or capacity. An ultra lightweight kernel is a collection of interrelated software functions that are small in number, size, and resource requirements such that they can be performed on elements of a fine-grain architecture such as the individual memory/processor nodes comprising a PIM-enabled system. Their delivered global capability is an emergent property derived from the synthesis of many mutually interacting local runtime functions, each contributing a small part of the operating or runtime system services. Memory management, task scheduling, exception handling, and active system reliability are all examples of system global services that are accomplished through the combined functionality of myriad ultra lightweight kernel actions distributed across a wide array of fine-grain PIM nodes. This presentation will discuss the distinguishing requirements and characteristics of ultra lightweight kernels that differentiate them from more conventional system software and will describe their basic logical functionality and organization.