Processing-in-memory (PIM) chips, which integrate processor logic into
memory devices, offer a new opportunity for bridging the growing gap
between processor and memory speeds, especially for applications with
high memory-bandwidth requirements. The Data-IntensiVe Architecture
(DIVA) system combines PIM memories with one or more external host
processors and a memory-to-memory interconnect. DIVA increases memory
bandwidth through two mechanisms: (1) performing selected computation
in memory, reducing the quantity of data transferred across the
processor-memory interface; and (2) providing communication mechanisms
called parcels for moving both data and computation throughout memory,
further bypassing the processor-memory bus. DIVA uniquely supports
in-memory acceleration of important irregular applications, including
sparse-matrix and pointer-based computations.
In this paper, we focus on several aspects of DIVA designed to effectively
support such computations at very high performance levels: (1) the memory
model and parcel definitions; (2) the memory-to-memory interconnect; and,
(3) requirements for the processor-to-memory interface. We demonstrate the
potential of PIM-based architectures in accelerating the performance of two
significant irregular com putations, sparse conjugate gradient and a
natural-join database operation.