Automatic Synthesis of Data Storage and Control Structures for FPGA-based Computing Engines

Pedro Diniz
University of Southern California
Information Sciences Institute
pedro@isi.edu

and

Joonseok Park
University of Southern California
Information Sciences Institute
joonseok@isi.edu

Abstract

Mapping computations written in high-level programming languages to FPGA-based computing engines requires programmers to create the datapath responsible for the core of the computation as well as the control structures to generate the appropriate signals to orchestrate its execution. This paper addresses the issue of automatic generation of data storage and control structures for FPGA-based reconfigurable computing engines using existing compiler data dependence analysis techniques. We describe a set of parameterizable data storage and control structures used as the target of our prototype compiler. We present a compiler analysis algorithm to derive the parameters of the data storage structures to minimize the required memory bandwidth of the implementation. We also describe a complete compilation scheme for mapping loops that manipulate multi-dimensional array variables to hardware. We present preliminary simulation results for complete designs generated manually using the results of the compiler analysis. These preliminary results show that is possible to successfully integrate compiler data dependence analysis with existing commercial synthesis tools.

Keywords:

FPGA-based reconfigurable computing architectures, compilation, program analysis, data queues.

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