Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines

Joonseok Park and Pedro Diniz
University of Southern California / Information Sciences Institute
4676 Admiralty Way, Suite 1001
Marina del Rey, California 90292
{joonseok,pedro}@isi.edu

Abstract

Multi-core reconfigurable architectures where soft-cores can be programmed over a reconfigurable substrate such as in an FPGA are a reality. For these target architectures it will become imperative that high-level mapping tools can synthesize and estimate the impact of high-level transformations in the overall design in terms of speed and area. The lack of support for external memory operations in current synthesis tools substantially increases the complexity and the burden on designers in the mapping of applications to FPGA-based computing engines. In this paper we address the problem of synthesizing and estimating the area and speed of memory interfacing for Static RAM (SRAM) and Synchronous Dynamic RAM (SDRAM) with various latency parameters and access modes. We describe a set of synthesizable and programmable memory interfaces a compiler can use to automatically generate the appropriate designs for mapping computations to FPGA-based architectures. Our preliminary results reveal that it is possible to accurately model the area and timing requirements using a linear estimation function. We have successfully integrated the proposed memory interface designs with simple image processing kernels generated using commercially available behavioral synthesis tools.

Keywords:

FPGA-based configurable computing; Hardware Interfaces and Memory Access Protocols, Estimation.

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