Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures

Pedro Diniz
University of Southern California / Information Sciences Institute
4676 Admiralty Way, Suite 1001
Marina del Rey, California 90292
pedro@isi.edu

Abstract

Fine-grain configurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs) offer ample opportunities for data reuse through application-specific storage structures, making them an ideal target for memory-intensive image/signal processing computations. In this paper we explore the area and time trade-off in terms of configurable resources and overall wall-clock time of several implementation schemes that exploit opportunities for data reuse using scalar replacement in fine-grain FPGAs. The preliminary results, on a Xilinx VirtexTM FPGA device, reveal that rotation-based solutions combined with predicated accesses tend to lead to higher-quality designs.

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