Performance and Area Modeling of Complete FPGA Designs in the presence
of Loop Transformations
Shayye Ragunhnatan
University of Southern California
Electrical Engineering Department - Systems Division
sraghuna@usc.edu
and
Joonseok Park
University of Southern California
Information Sciences Institute
joonseok@isi.edu
and
Pedro Diniz
University of Southern California
Information Sciences Institute
pedro@isi.edu
Abstract
Selecting which program transformations to apply when
mapping computations to FPGA-based architectures
leads to prohibitively long design exploration cycles.
An alternative is to develop fast, yet accurate, performance
and area models to understand the impact and interaction
of the transformations.
In this paper we present a combined analytical performance
and area modeling for complete FPGA
designs in the presence of loop transformations.
Our approach takes into account the impact of input/output
memory bandwidth and memory interface resources, often
the limiting factor in the effective implementation of these
computations.
Our preliminary results reveal that our modeling is very
accurate allowing a compiler tool to quickly explore a
very large design space resulting in the selection of a
feasible high-performance design.