Synthesis of Memory Access Controller for Streamed Data Applications for FPGA-based Computing Engines

Joonseok Park
University of Southern California
Information Sciences Institute
joonseok@isi.edu

and

Pedro Diniz
University of Southern California
Information Sciences Institute
pedro@isi.edu

Abstract

Commercially available behavioral synthesis tools do not adequately support vendor-specific memory interfaces, and in particular do not provide direct support for pipelined access modes, increasing the complexity and the burden on designers in the mapping of applications to FPGA-based computing engines. In this paper we address the problem of memory access interfacing and aggressive scheduling of memory accesses by proposing a decoupled architecture with two components - one component captures the specific target architecture timing while the other component uses application specific memory access pattern information. The results presented in this paper support the claim that it is possible to exploit application specific information and integrate that knowledge in a custom schedulers that mix pipelined access modes and non-pipelined access modes for reducing the overhead associated with memory accesses. The results also reveal that the additional design complexity of the scheduler, and its impact in the overall design is minimal.

Keywords:

FPGA-based configurable computing; Scheduling of memory accesses; Hardware Interfaces and Customizable Memory Controllers.

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