NAND gate hspice file

*enables awaves processing
.options post

.model NCHAN NMOS (VTO=0.5, KP=50u)
.model PCHAN PMOS (VT0=-0.5, KP=20u) 

*VDD
V1 1 0 3.3

*Input 1 (and 2)
V2 2 0 0

*Two P-types in Parallel
M1 4 2 1 1 PCHAN W=5u L=1u
M2 4 2 1 1 PCHAN W=5u L=1u

*Two N-types in Series
M3 4 2 5 0 NCHAN W=2u L=1u
M4 5 2 0 0 NCHAN W=2u L=1u

*Step the voltage V2 from 0 to 3.3
.dc V2 START=0 STOP=3.3 STEP=.01

.op

*Vin is at node 2
*Vout is at node 4
*Graph V2 on the X-axis
*Graph V4 on the Y-axis


*A nand gate with inputs tied together acts like
*an inverter so you should see an inverter transfer
*characteristic

.end