NOR gate hspice file

*enables awaves processing
.options post

.model NCHAN NMOS (VTO=0.5, KP=50u)
.model PCHAN PMOS (VT0=-0.5, KP=20u) 

*VDD
V1 1 0 3.3

*Input 1 (and 2)
V2 2 0 PULSE (0 3.3 0 0 0 5n 10n)

*Two P-types in Series
M1 3 2 1 1 PCHAN W=5u L=1u
M2 4 2 3 1 PCHAN W=5u L=1u

*Two N-types in Parallel
M3 4 2 0 0 NCHAN W=2u L=1u
M4 4 2 0 0 NCHAN W=2u L=1u

C1 4 0 200f

.op

*Vin is at node 2
*Vout is at node 4
*Graph V4 on the Y-axis

.tran 10p 20n

*A nor gate with inputs tied together acts like
*an inverter

*The capacitor allows you to see rise/fall
*propagation times

.end