Selected Publications

Following is a sampling of recent publications – spanning security, trust, reliance and reliability – by SURE researchers.

2015

I. S. Esqueda and C. D. Cress, "Modeling Radiation-Induced Scattering in Graphene," IEEE Trans. Nucl. Sci., in press, 2015.

I. S. Esqueda, H. J. Barnaby, M. P. King, "Compact modeling of total ionizing dose and aging effects in MOS technologies," IEEE Trans. Nucl. Sci., vol. 62, No. 4, pp. 1501-1515, 2015.

I. S. Esqueda, C. D. Cress, Y. Cao, Y. Che and C. Zhou, "The impact of defect scattering on the quasi-Ballistic transport of nanoscale conductors," Journal of Applied Physics, 117, 084319, 2015.

I. S. Esqueda, "The impact of stress-induced defects on MOS electrostatics and short-channel effects," Journal of Solid State Electronics, 103, pp. 167-172, 2015.

2014

Zick, Kenneth M., Li, S., French, M., "High-precision self-characterization for the LUT burn-in information leakage threat," In International Conference on Field Programmable  Logic and Applications (FPL), 2014.

K. Zick, F. Spedalieri and M. French, "Physical Variations and the Promise of Adaptive Embedding," poster, Adiabatic Quantum Computing Workshop, June 2014.

A Power Efficient Reconfigurable System-in-Stack: 3D Integration of Accelerators, FPGAs, and DRAM," Peter Gadfort, Aravind Dasu, Ali Akoglu, Yoon Kah Leow, and Michael Fritze. System-on-Chip Conference (SOCC), 2014 27th IEEE International, vol., no., pp.11,16, 2-5 Sept. 2014.

Y. Pino, V. Jyothi, and M. French, "Intra-Die Process Variation Aware Anomaly Detection in FPGAs", International Test Conference (ITC), Seattle, WA, Oct 21 - 23 2014.

I. S. Esqueda, C. D. Cress, Y. Che, Y. Cao and C. Zhou, "Charge trapping in aligned single-walled carbon nanotube arrays induced by ionizing radiation exposure," Journal of Applied Physics, 115, 054506, 2014.

I. S. Esqueda and H. J. Barnaby, "A defect-based compact modeling approach for the reliability of CMOS devices and integrated circuits," Journal of Solid State Electronics , 91, pp. 81-86, 2014.

2013

Walters, J.P., Zick, K.M., French, M., "A Practical Characterization of a NASA SpaceCube Application through Fault Emulation and Laser Testing," In IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013.

F. Kashfi and J. Draper, "Multiobjective Optimization of Cost, Performance and Thermal Reliability in 3DICs," in 2013 Euromicro Conference on Digital System Design (DSD) , 2013, pp. 404-411

G. Neela and J. Draper, "Logic-on-logic partitioning techniques for 3-dimensional integrated circuits," in Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS) , 2013, pp. 789-792

R. Soni, N. Steiner, M. French, "Open-Source Bitstream Generation," IEEE Field Programmable Custom Computing Machines, Seattle, WA, April 2013.

K. Zick, M. Srivastav, W. Zhang, M. French, "Sensing FPGA Voltage Transients and Protecting Against Power Supply-Related Attacks," ACM International Symposium on FPGAs, Monterey CA, 2013.

2011

A. Schmidt, B. Huang, R. Sass, and M. French, "Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAs," IEEE Field Programmable Custom Computing Machines, Salt Lake City, UT, May 2011.

N. Steiner, A. Wood, H. Shojaei, J. Couch, P. Athanas, M. French, "Torc: Tools for Open Reconfigurable Computing," 19th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February, 2011.

2010

A. Schmidt, W. Kritikos, R. Sass, E. Anderson, and M. French, "Merging Programming Moldels and On-chip Networks to Meet the Programmable and Performance Needs of Multi-Core Systems on a Programmable Chip," IEEE International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, December 2010. BEST PAPER AWARD

Mahta Haghi and Jeff Draper, A Single-Event Upset Hardening Technique for High Speed MOS Current Mode Logic, Proceedings of the IEEE International Symposium on Circuits and Systems, June 2010.

Young Hoon Kang, Taek-Jun Kwon, Jeff Draper, Fault-Tolerant Flow Control in On-Chip Networks, Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip, May 2010

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