Event Details

Through its computing power provided by GPUs, Moore’s Law has been at the core of the present deep learning and ML revolution. Nevertheless, given the increasing complexity of AI algorithms, the current hardware platforms fail to provide the required speed and power efficiency. For example, the computing efficiency for decades has been doubling every two years compared to the recent increase in compute requirements from ML algorithms that are doubling every 3.4 months. This vast discrepancy stems from the inherent bottlenecks present in the Silicon computing eco-system. A typical hardware platform consists of three broad components – a memory storage unit, processing units, and interconnect bus. All these three components are limited in terms of achievable bandwidth and memory bottleneck.

In this talk, I will present solutions addressing each of these components. Specifically, I would discuss how existing and alternate memory technologies can provide storage density and speed beyond present technology. Additionally, the memory to processor communication bottleneck can be significantly mitigated by using emerging concepts like processing-in-memory. Further, the scale of computing systems can also be dramatically increased by using a wafer-scale chip integration using on-chip optical interconnects for creating IC that is 50x larger than the largest available GPUs. These innovations are bought in by close co-optimization of materials, devices, circuits, and computer architectures. This cross-layer co-optimization also opens new avenues for hardware-algorithm co-design geared towards cloud and edge-based intelligent computing systems.

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Speaker Bio

Ajey Jacob is the director of the Application Specific Intelligent Computing (ASIC) Lab, a research group at the Information Sciences Institute (ISI), University of Southern California. Ajey Jacob brings 16 years of industry research, development, and manufacturing experience from Intel Corporation and GLOBAFOUNDRIES (GF) to ISI. Ajey primarily focuses on materials, devices, and integration aspects of the technology. Before joining ISI in October 2019, Ajey Jacob started and managed its differentiating technology research group for the GF worldwide R&D. In this capacity, Ajey Jacob researched More than Moore differentiating and disruptive elements such as silicon photonics, non-volatile memory (MRAM, FeRAM, RRAM), for a plethora of applications such as transceivers, embedded memory, advanced logic, neuromorphic computing at its advanced fab in Malta, NY. Dr. Jacob has also served GF in various other capacities such as leading the exploratory device and integration research group (sub 14 nm technology node), and the pathfinding integration research program (10 & 7 nm node) for the IBM Alliance in Albany, NY. Until 2011, Ajey Jacob worked as a senior research scientist for Intel corporation’s component research organization. At Intel, Ajey managed two industry-sponsored strategic research consortia for next-generation CMOS devices and materials “Western Institute of Nanoelectronics” (WIN) and “Functional Engineering in Nano Architectonics” (FENA) and many other Intel-sponsored research projects. Ajey Jacob has also been a device engineer supporting the high-volume manufacturing of the 90 nm technologies at Intel and 28 nm technology at GLOBALFOUNDRIES.

Ajey Jacob received his Ph.D. in Physics from the Chalmers University of Technology/Gothenburg University, Gothenburg, Sweden, in 2002. Ajey Jacob has more than 150 USPTO issued/accepted patents, more than 50 patents pending approval from USPTO. He has also published three book chapters, more than 75 journals, and conference papers in a wide area of scaled and differentiating technologies.

At GF, Ajey Jacob was conferred the tile of Master Inventor from the years 2017 to 2020. In 2013’ and 2016’ Semiconductor Research Corporation (SRC) awarded Ajey Jacob with the Mahboob Khan Outstanding Industry Liaison Award. Ajey Jacob is currently serving as a committee member for the IEEE Electronics Components and Technology Conference (ECTC) Silicon Photonics Session and International Conference on Frontiers of Characterization and Metrology for Nanoelectronics (FCMN). Ajey Jacob is also the co-chair for the MIT/AIM Photonics monolithic integration session of the Integrated Photonics Systems Roadmap (IPSR).