Stephen P. Crago

Fault Tolerant Computing on Maestro

TitleFault Tolerant Computing on Maestro
Publication TypeConference Paper
Year of Publication2010
AuthorsS. P. Crago, and J. P. Walters
Conference NameFault-Tolerant Spaceborne Computing Employing New Technologies
Date Published05/2010
Conference LocationAlburquerque, New Mexico
Abstract

The microprocessor trend towards multi-core and many-core means that redundant resources are getting inexpensive and can be used for both computation and increased capabilities, including fault tolerance. Because multi-core architectures have an inherent programmable redundancy, multi-core processors can support flexible, software-implemented fault tolerance. The Maestro processor, which has been implemented with rad-hard by design technology, has 49 cores, as well as redundant inter-core networks and chip interfaces. In this talk, we explore a range of fault tolerance techniques that can be used on Maestro and other multi-core and many-core architectures and identify other challenges that have not yet been addressed.

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