Vivek V Menon

Design and Performance Measurement of a High-Performance Computing Cluster

TitleDesign and Performance Measurement of a High-Performance Computing Cluster
Publication TypeConference Paper
Year of Publication2012
AuthorsK. George, and V. Venugopalan
Conference NameIEEE International Instrumentation and Measurement Technology Conference (I2MTC)
Date PublishedMay
Abstract

Graphics processor units (GPU) are specialized hardware accelerators that can be utilized for computations needing high parallelism and high memory bandwidth. Propelled by the attractive Flops/$ ratio and its capability to outperform a CPU cluster at the equivalent cost, large-scale GPU clusters are gaining popularity in the high-performance computing (HPC) community. However, the design challenges associated with the setup and application development process for an efficient HPC cluster includes: a) data movement and locality on the hardware accelerators; b) task mapping and allocation; and c) setting up a well-balanced system. In this paper, we present our experience setting up a GPU cluster for HPC applications; particularly signal processing for digital wideband receivers. We describe the architecture, hardware and software platform of the proposed cluster. The proposed GPU cluster implementing a 1.25 GHz digital wideband receiver was compared and contrasted against a HPC based predecessor receiver system. The adaptability of the GPU cluster was further demonstrated by utilizing it for a multiple receiver implementation that demanded higher data processing capability and throughput.

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