Vivek V Menon

Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors

TitleHardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors
Publication TypeConference Paper
Year of Publication2013
AuthorsV. Venugopalan, and D. M. Shila
Conference NameProceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays
Date PublishedFebruary
Conference LocationNew York, NY, USA
Abstract

Field programmable gate arrays (FPGA) are extensively used for rapid prototyping in embedded system applications. While hardware acceleration can be done via specialized processors like a Graphical Processing Unit (GPU), they can also be accomplished with FPGAs for more specialized scenarios. GPUs essentially consist of massively parallel cores and have high memory bandwidth; FPGAs, on the other hand, provide flexibility in terms of customizable I/O and computational resources. In this paper, we explore the usage of GPUs and FPGAs as cryptographic co-processors in streaming dataflow systems with huge rate of data inhalation. Two classic lightweight encryption algorithms, Tiny Encryption Algorithm (TEA) and Extended Tiny Encryption Algorithm (XTEA), are targeted for implementation on GPUs and FPGAs. The GPU implementations of TEA and XTEA in this study depict a maximum speedup of 13x over CPU based implementation. The pipelined FPGA implementation is able to realize a throughput of 6-9x more than the GPU for small plaintext sizes.

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