Computational Systems and Technology

Heterogeneous Accelerator Testbed

Over the past year the Reconfigurable Computing Group at the University of Southern California’s Information Sciences Institute (USC/ISI) and the FPGA/Parallel Computing Group at USC have been working collaboratively as part of Intel’s Heterogonous Accelerator Research Program (informally known as HARP). Intel developed HARP to enable research across hardware and software for performance of diverse workloads in the data center as computer architectures move beyond homogeneous parallelism to incorporate application-customized hardware. USC/ISI was selected as one of three Universities to receive the new HARP 2.0 platform which includes an Intel Xeon Processor and Arria10 FPGA integrated within the same device package. The USC/ISI team has a combined sixteen graduate students, research staff, and faculty members from USC/ISI using the shared resource across research topics including image processing, distributed big data and graph analytics, natural language processing, software-defined networking, and memory access utilization and optimization. To date the work has resulted in five publications, four invited talks and demonstrations and two posters, with impressive results in natural language processing (170x speedup), deep learning (5x), high-throughput sorting (2-5x), and 5.8x speedup in Convolutional Neural Networks (CNN) classification on FPGAs. Most recently, HARP is providing a research platform for Project Volcan which aims to bridge the gap between next generation memory architectures and high performance computing platforms.

USC/ISI's FPGA Testbed