Independant Functional Testing of Commercial FPGA Devices


Interconnect Testing

Custom massively replicatable paths to exercise PIPs: one signal exiting to left and
another signal arriving from right, passing through PIPs

Logic Testing

Paths through configurable logic
Flip-flop on right enables launch and capture of test
signals through logic

Runtime Optimization

Utilize techniques such as partial runtime reconfiguration to reduce runtime


Functional testing of commercial FPGAs, independent of in-house FPGA vendor production testing, is an important first step in establishing a trusted supply-chain, determining the usability of devices stored in inventory for long periods of time, verifying complex 2.5D and 3D packages, and determining the health status of fielded systems. Independent functional testing of the FPGA VLSI provides an open, transparent check that the device is in fact the device it claims to be and is in good working order. This is no trivial feat as modern FPGA devices now contain over 10B transistors, over a dozen types of Hard IP, 35M user wires, and 380M user routing switches.

IFT is researching algorithmic generation of independent functional tests that can be used to cross-check the FPGA manufacturer’s testing and can also be used for field testing of counterfeit, damaged, or aging parts. Stuck at fault testing is utilized to detect failures on all routing and Slice interconnect paths, and hard IP functionality (Slices, BRAMs, DSPs, …). Modified Algorithmic Test Sequence (MATS) is used to test memory storage for BRAMs and configuration cells. Additional research is being conducted to expand the scope and fidelity of the tests involved. IFT utilizes FPGA device databases to concretely track and provide testing coverage metrics.

The material is based on research sponsored by the Navy, Air Force Research Labs (AFRL), and the Defense Advanced Projects Agency (DARPA) under agreement number FA8650-18-1-7817. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the Navy, Air Force Research Labs (AFRL), the Defense Advanced Projects Agency (DARPA), or the U.S. Government. This work is also supported by generous donations from Synopsys and Cadence.