{"id":332,"date":"2022-11-18T16:27:00","date_gmt":"2022-11-18T16:27:00","guid":{"rendered":"https:\/\/www.isi.edu\/research-groups-rcg\/?page_id=332"},"modified":"2023-10-03T14:22:14","modified_gmt":"2023-10-03T14:22:14","slug":"rhino","status":"publish","type":"page","link":"https:\/\/www.isi.edu\/research-groups-rcg\/projects\/historical-projects\/rhino\/","title":{"rendered":"RHinO: Reconfigurable Hardware in Orbit"},"content":{"rendered":"\r\n<section>\r\n<h2>Overview<\/h2>\r\n<\/section>\r\n<p><img loading=\"lazy\" decoding=\"async\" title=\"rhino_brick\" src=\"https:\/\/www.isi.edu\/research-groups-rcg\/wp-content\/uploads\/sites\/17\/2022\/11\/rhino_brick.gif\" alt=\"rhino_brick\" width=\"451\" height=\"216\" \/><\/p>\r\n<p>The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multi-mission reconfigurable space processors using SRAM-based FPGAs.<\/p>\r\n<p><img decoding=\"async\" src=\"https:\/\/www.isi.edu\/research-groups-rcg\/wp-content\/uploads\/sites\/17\/2022\/11\/jhdl.jpg\" \/><\/p>\r\n<h3>JHDL Backbone<\/h3>\r\n<p>Using the well establsihed JHDL infrastructure, we are adding tools and viewers that allow an FPGA application designer to better consider radiation mitigation and power minimization.<\/p>\r\n<p><img decoding=\"async\" src=\"https:\/\/www.isi.edu\/research-groups-rcg\/wp-content\/uploads\/sites\/17\/2022\/11\/seu.jpg\" \/><\/p>\r\n<h3>SEU Effects<\/h3>\r\n<p>We are developing a scalable, open API-based SEU emulator, capable of testing configurations. We have also developed a half-latch mitigation tool.<\/p>\r\n<p><img decoding=\"async\" src=\"https:\/\/www.isi.edu\/research-groups-rcg\/wp-content\/uploads\/sites\/17\/2022\/11\/power.jpg\" \/><\/p>\r\n<h3>Power<\/h3>\r\n<p>In the power domain, we have developed tools to visualize dynamic power consumption and judge the quality of place and route iterations in terms of power. Future research will be on tools to optimize power utilizing this information.<\/p>\r\n<p><img decoding=\"async\" src=\"https:\/\/www.isi.edu\/research-groups-rcg\/wp-content\/uploads\/sites\/17\/2022\/11\/self-repair.jpg\" \/><\/p>\r\n<h3>Self Repair<\/h3>\r\n<p>Our tools are also supporting hooks to allow evolvable algorithm techniques to re-route around hard faults in-orbit.<\/p>\r\n<p>.intro-info .box{ margin: 30px 0 15px 0px; } .intro-info .border{ border: 0.125rem solid #dee2e6 !important; } .intro-info .image{ text-align: center; margin-bottom: 15px; width: 100%; } .intro-info .text{ font-weight: 200; max-width: 600px; display: block; margin: 0 auto 15px auto; } .intro-info .col-xl &gt; div { height: 100%; border-radius: 1rem; overflow: hidden; }<\/p>\r\n<section>\r\n<h2>Research Partners<\/h2>\r\n<\/section>\r\n<p><a href=\"https:\/\/www2.et.byu.edu\/reliability\/\" target=\"_blank\" rel=\"noopener\"> <img loading=\"lazy\" decoding=\"async\" title=\"byue\" src=\"https:\/\/www.isi.edu\/research-groups-rcg\/wp-content\/uploads\/sites\/17\/2022\/11\/byue.jpg\" alt=\"byue\" width=\"300\" height=\"100\" \/> <\/a> <a href=\"https:\/\/www.lanl.gov\/\" target=\"_blank\" rel=\"noopener\"> <img loading=\"lazy\" decoding=\"async\" title=\"lanl\" src=\"https:\/\/www.isi.edu\/research-groups-rcg\/wp-content\/uploads\/sites\/17\/2022\/11\/lanl.jpg\" alt=\"lanl\" width=\"300\" height=\"100\" \/> <\/a> <a href=\"https:\/\/www.nasa.gov\/ames\" target=\"_blank\" rel=\"noopener\"> <img loading=\"lazy\" decoding=\"async\" title=\"arc-nasa\" src=\"https:\/\/www.isi.edu\/research-groups-rcg\/wp-content\/uploads\/sites\/17\/2022\/11\/arc-nasa.jpg\" alt=\"arc-nasa\" width=\"300\" height=\"100\" \/> <\/a><\/p>\r\n","protected":false},"excerpt":{"rendered":"<p>Overview The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating&hellip;<\/p>\n","protected":false},"author":421,"featured_media":0,"parent":290,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"news_source":"","news_author":"","external_news_link":"","footnotes":""},"class_list":["post-332","page","type-page","status-publish","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.2 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>RHinO: Reconfigurable Hardware in Orbit - Reconfigurable Computing Group<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.isi.edu\/research-groups-rcg\/projects\/historical-projects\/rhino\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"RHinO: Reconfigurable Hardware in Orbit - Reconfigurable Computing Group\" \/>\n<meta property=\"og:description\" content=\"Overview The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. 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