Application Specific Intelligent Computing Laboratory (ASIC)

PATENTS

 

 

  1. [PATENT] Backup and/or Restore of a Memory Circuit AR Jaiswal, M Bhargava, GM Lattimore US Patent App. 16/167,822, 2020
  2. [PATENT] MRAM read and write methods using an incubation delay interval AR Jaiswal, M Bhargava US Patent 10,593,397, 2020
  3. [PATENT] Composite waveguiding structures including semiconductor fins Y Bian, A Thomas, AP Jacob US Patent 10,670,804, 2020
  4. [PATENT] Waveguide structures AP Jacob, MVS Dahlem, H Zafar, A Khilo, S Chandran US Patent App. 16/199,468, 2020
  5. [PATENT] Switchable and reconfigurable grating couplers Y Bian, AP Jacob US Patent App. 16/199,811, 2020
  6. [PATENT] Resistive nonvolatile memory cells with shared access transistors AP Jacob, A Agrawal, BC PaulUS Patent 10,665,281, 2020
  7. [PATENT] Electro-optic modulators with stacked metal, dielectric, and active layers Y Bian, AP Jacob, A Thomas US Patent 10,649,245, 2020
  8. [PATENT] Back-end-of-line blocking structures arranged over a waveguide core Y Bian, AP Jacob, A Thomas US Patent 10,649,140, 2020
  9. [PATENT] Polarizers and polarization splitters phase-matched with a back-end-of-line layer Y Bian, AP Jacob, A Thomas - US Patent 10,641,956, 2020
  10. [PATENT] Multiple-layer arrangements using tunable materials to provide switchable optical components Y Bian, A Thomas, AP Jacob US Patent 10,585,245 2020
  11. [PATENT] Method, system and device for integration of volatile and non-volatile memory bitcells AR Jaiswal, M Bhargava US Patent App. 16/201,080
  12. [PATENT] Memory device having in-situ in-memory stateful vector logic operation AR Jaiswal, A Agrawal, K Roy US Patent App. 16/265,024
  13. [PATENT] Slot assisted grating based transverse magnetic (TM) transmission mode pass polarizer AP Jacob, MVS Dahlem, H Zafar, A Khilo, S Chandran US Patent 10,557,989 2020
  14. [PATENT] Stacked waveguide arrangements providing field confinement Y Bian, AP Jacob US Patent App. 16/040,896 2020
  15. [PATENT] Waveguide bends with mode-confining structures Y Bian, AP Jacob US Patent App. 16/026,596 2020
  16. [PATENT] Magneto-resistive memory structures with improved sensing, and associated sensing methods A Jaiswal, AP Jacob, BC Paul, W Taylor, DPC Shum US Patent 10,515,679 2019
  17. [PATENT] Integrated circuits having memory cells with shared bit lines and shared source lines BC Paul, A Jaiswal, AP Jacob, W Taylor, DPC Shum US Patent 10,510,392 2019
  18. [PATENT] Grating couplers with multiple configurations AP Jacob, Y Bian US Patent App. 16/000,249 2019
  19. [PATENT] Integrated circuits with look up tables, and methods of producing and operating the same A Jaiswal, AP Jacob US Patent 10,468,083 2019
  20. [PATENT] Logic-in-memory computations for non-volatile resistive random access memory (RAM) array AR Jaiswal, AP Jacob US Patent 10,468,084 2019
  21. [PATENT] Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for differential bit operation and methods for fabricating the same AP Jacob, J Akhilesh US Patent 10,468,456 2019
  22. [PATENT] Methods, apparatus, and manufacturing system for forming source and drain regions in a vertical field effect transistor AP Jacob, XA Tran, H Zang, B Haran, S Kalaga US Patent 10,461,173 2019
  23. [PATENT] Finfet with multilayer fins for multi-value logic (mvl) applications and method of forming MH Chi, A Jacob, A Paul US Patent App. 16/433,626 2019
  24. [PATENT] Stacked elongated nanoshapes of different semiconductor materials and structures that incorporate the nanoshapes BJ Pawlak, G Bouche, AP Jacob US Patent 10,453,750 2019
  25. [PATENT] Waveguides including a patterned dielectric layer Y Bian, A Thomas, AP Jacob, KJ Giewont, K Nummy, A Stricker, B Peng US Patent 10,444,433 2019
  26. [PATENT] Grating couplers with cladding layer (s) AP Jacob, Y Bian US Patent App. 15/945,347 2019
  27. [PATENT] Waveguide bends with field confinement Y Bian, AP Jacob US Patent 10,436,982 2019
  28. [PATENT] Polarization splitters based on stacked waveguides A Thomas, Y Bian, AP Jacob US Patent 10,429,581 2019
  29. [PATENT] Waveguide-to-waveguide couplers with multiple tapers Y Bian, AP Jacob, SM Shank US Patent 10,429,582 1 2019
  30. [PATENT] Integrated graphene detectors with waveguides AP Jacob US Patent App. 16/438,863 2019
  31. [PATENT] Integrated circuits including magnetic random access memory structures and methods for fabricating the same AP Jacob, J Akhilesh US Patent 10,411,069 2019
  32. [PATENT] FinFETs for light emitting diode displays AP Jacob, S Banna, D Nayak US Patent 10,396,121 2019
  33. [PATENT] Light emitting diodes (LEDs) with stacked multi-color pixels for displays S Banna, D Nayak, AP Jacob US Patent 10,388,691 2019
  34. [PATENT] FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming MH Chi, A Jacob, A Paul US Patent 10,388,790 2019
  35. [PATENT] Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for dual bit operation and methods for fabricating the same AP Jacob, J Akhilesh US Patent 10,381,406 2019
  36. [PATENT] Integrated graphene detectors with waveguides AP Jacob US Patent 10,374,106 1 2019
  37. [PATENT] Silicon nitride grating couplers AP Jacob, Y Bian US Patent App. 15/878,025 2019
  38. [PATENT] Integrated vertical transistors and light emitting diodes AP Jacob, DK Nayak, SR Banna US Patent 10,355,043 2019
  39. [PATENT] Graphene contacts on source/drain regions of FinFET devices AP Jacob US Patent 10,325,812 2019 Light emitting diodes (LEDs) with integrated CMOS circuits D Nayak, S Banna, AP Jacob US Patent 10,283,560 2019
  40. [PATENT] Light emitting diodes AP Jacob, S Banna, D Nayak US Patent 10,263,151 2019
  41. [PATENT] Non-planar waveguide structures AP Jacob US Patent App. 15/725,524 2019
  42. [PATENT] Grating couplers with multiple configurations AP Jacob, Y Bian US Patent 10,241,269 2019
  43. [PATENT] Light emitting diode structures DK Nayak, SR Banna, AP Jacob US Patent 10,217,900 2019
  44. [PATENT] Uniform semiconductor nanowire and nanosheet light emitting diodes DK Nayak, SR Banna, AP Jacob US Patent App. 15/678,385 2019
  45. [PATENT] Multiple directed self-assembly material mask patterning for forming vertical nanowires S Bentley, RA Farrell, G Schmid, AP Jacob US Patent 10,186,577 13 2019
  46. [PATENT] Methods of forming NMOS and PMOS finFET devices and the resulting product AP Jacob US Patent 10,056,300 2018
  47. [PATENT] Programmable via devices with metal/semiconductor via links and fabrication methods thereof AP Jacob, SK Patil, MH Chi US Patent 10,056,331 2018
  48. [PATENT] Semiconductor wafers with reduced bow and warpage AP Jacob, SR Banna, DK Nayak, BJ Pawlak US Patent 10,056,453 2018
  49. [PATENT] Methods of forming fin isolation regions under tensile-strained fins on FinFET semiconductor devices AP Jacob, MK Akarvardar, JA Fronheiser US Patent 10,026,659 9 2018
  50. [PATENT] Methods of forming graphene contacts on source/drain regions of FinFET devices AP Jacob US Patent 9,972,537 12 2018
  51. [PATENT] Common fabrication of multiple FinFETs with different channel heights MK Akarvardar, JA Fronheiser, AP Jacob US Patent 9,960,257 1 2018
  52. [PATENT] Method for forming nanowires including multiple integrated devices with alternate channel materials AP Jacob US Patent 9,953,882 2018
  53. [PATENT] Multiwidth finFET with channel cladding R Xie, AP Jacob US Patent 9,954,104 11 2018
  54. [PATENT] LEDs with three color RGB pixels for displays S Banna, D Nayak, AP Jacob US Patent 9,941,330 2 2018
  55. [PATENT] Light emitting diodes (LEDs) with integrated CMOS circuits D Nayak, S Banna, AP Jacob US Patent 9,941,329 4 2018
  56. [PATENT] Silicon waveguide devices in integrated photonics RA Augur, AP Jacob, SM Shank US Patent 9,864,132 2018
  57. [PATENT] Non-planar monolithic hybrid optoelectronic structures and methods AP Jacob US Patent 9,864,136 1 2018
  58. [PATENT] Directed self-assembly material etch mask for forming vertical nanowires S Bentley, RA Farrell, G Schmid, AP Jacob US Patent 9,865,682 2018
  59. [PATENT] Forming a silicon based layer in a trench to prevent corner rounding AP Jacob, J Fronheiser, B Doris, H Bu US Patent App. 15/198,570 2018
  60. [PATENT] Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide MK Akarvardar, AP Jacob US Patent 9,842,897 2017
  61. [PATENT] Method for forming nanowires including multiple integrated devices with alternate channel materials AP Jacob US Patent 9,831,131 1 2017
  62. [PATENT] Programmable via devices with metal/semiconductor via links and fabrication methods thereof AP Jacob, SK Patil, MH Chi US Patent 9,812,393 2017
  63. [PATENT] Methods of forming PMOS and NMOS FinFET devices on CMOS based integrated circuit products AP Jacob US Patent 9,799,767 7 2017
  64. [PATENT] Vertical nanowires formed on upper fin surface S Bentley, RA Farrell, G Schmid, AP Jacob US Patent App. 15/598,905 2017
  65. [PATENT] Heterogeneous integration of 3D Si and III-V vertical nanowire structures for mixed signal circuits fabrication SK Patil, AP Jacob US Patent 9,754,843 2017
  66. [PATENT] Semiconductor structure with anti-efuse device SK Patil, MH Chi, AP Jacob US Patent 9,754,903 2017
  67. [PATENT] Methods of forming PMOS FinFET devices and multiple NMOS FinFET devices with different performance characteristics AP Jacob US Patent 9,748,387 7 2017
  68. [PATENT] Methods of forming NMOS and PMOS FinFET devices and the resulting product AP Jacob US Patent 9,741,622 7 2017
  69. [PATENT] Electrical isolation of FinFET active region by selective oxidation of sacrificial layer MK Akarvardar, JA Fronheiser, AP Jacob US Patent 9,716,174 33 2017
  70. [PATENT] On-chip variable capacitor with geometric cross-section S Patil, AP Jacob, SM Pandey US Patent App. 14/987,211 2017
  71. [PATENT] Directed self-assembly material growth mask for forming vertical nanowires S Bentley, RA Farrell, G Schmid, AP Jacob US Patent 9,698,025 1 2017
  72. [PATENT] Programmable devices with current-facilitated migration and fabrication methods SK Patil, MH Chi, AP Jacob US Patent 9,691,497 2017
  73. [PATENT] Fin isolation structures facilitating different fin isolation schemes AP Jacob, K Cheng, B Doris, N Loubet, P Khare, R Divakaruni US Patent 9,673,222 2017
  74. [PATENT] Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material AP Jacob, B Doris, K Cheng, A Khakifirooz, K Rim US Patent 9,673,083 8 2017 Folded ballistic conductor interconnect line AP Jacob US Patent 9,633,947 1 2017
  75. [PATENT] FinFET device including a dielectrically isolated silicon alloy fin AP Jacob US Patent 9,634,123 6 2017
  76. [PATENT] Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device AP Jacob, B Doris, K Cheng, N Loubet US Patent 9,627,245 11 2017
  77. [PATENT] Methods of forming low defect replacement fins for a FinFET semiconductor device and the resulting devices J Fronheiser, AP Jacob, WP Maszara, K Akarvardar US Patent 9,614,058 2017
  78. [PATENT] Methods of modulating strain in PFET and NFET FinFET semiconductor devices AP Jacob, MK Akarvardar, B Doris, A Khakifirooz US Patent 9,589,849 2017
  79. [PATENT] Methods of forming fins for a FinFET device by forming and replacing sacrificial fin structures with alternative materials MK Akarvardar, AP Jacob US Patent 9,590,040 2 2017
  80. [PATENT] Methods for fabricating programmable devices and related structures SK Patil, AP Jacob, MH Chi US Patent 9,564,447 2017
  81. [PATENT] Self-aligned dual-height isolation for bulk FinFET MK Akarvardar, SJ Bentley, K Cheng, BB Doris, J Fronheiser, AP Jacob, ... US Patent 9,564,486 2017
  82. [PATENT] Methods of forming different FinFET devices with different threshold voltages and integrated circuit products containing such devices AP Jacob, WP Maszara, K Akarvardar US Patent 9,564,367 20 2017
  83. [PATENT] Methods of removing portions of fins by preforming a selectively etchable material in the substrate Y Qi, AP Jacob US Patent 9,524,908 14 2016
  84. [PATENT] Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel region AP Jacob, WP Maszara, JA Fronheiser US Patent 9,508,853 4 2016
  85. [PATENT] Semiconductor devices with dummy gate structures partially on isolation regions R Xie, X Cai, AP Jacob, A Knorr, C Prindle US Patent 9,496,354 3 2016
  86. [PATENT] Non-planar exciton transistor (BiSFET) and methods for making AP Jacob US Patent 9,484,428 1 2016
  87. [PATENT] FinFET device including a uniform silicon alloy fin AP Jacob, JA Fronheiser, Y Qi, S Mignot US Patent 9,478,663 6 2016
  88. [PATENT] Uniaxially-strained fd-soi finfet P Morin, M Vinet, L Grenouillet, AP Jacob US Patent 9,466,664 2016
  89. [PATENT] Finfet semiconductor devices with stressed channel regions X Cai, R Xie, K Cheng, A Khakifirooz, AP Jacob, WP Maszara US Patent App. 15/186,632 2016
  90. [PATENT] Methods of forming strained and relaxed germanium fins for PMOS and NMOS finFET devices, respectively AP Jacob US Patent 9,455,199 1 2016
  91. [PATENT] Methods of forming doped epitaxial SiGe material on semiconductor devices AP Jacob, JA Fronheiser, MK Akarvardar US Patent 9,455,140 2016
  92. [PATENT] Controlled junction transistors and methods of fabrication SJ Bentley, AP Jacob, CY Chen, T Yamashita US Patent App. 15/154,495 2016
  93. [PATENT] Methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of material and by performing a fin-trimming process AP Jacob, B Doris, K Cheng, A Khakifirooz, K Rim US Patent 9,431,306 6 2016
  94. [PATENT] FinFET semiconductor device with isolated fins made of alternative channel materials AP Jacob, MK Akarvardar US Patent 9,425,315 2 2016
  95. [PATENT] Methods of forming alternative channel materials on FinFET semiconductor devices AP Jacob, MK Akarvardar US Patent 9,425,289 8 2016
  96. [PATENT] Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device X Cai, R Xie, K Cheng, A Khakifirooz, AP Jacob, WP Maszara US Patent 9,412,822 24 2016
  97. [PATENT] FinFET device including a uniform silicon alloy fin AP Jacob, JA Fronheiser, MK Akarvardar, S Bentley US Patent 9,406,803 1 2016
  98. [PATENT] Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide MK Akarvardar, AP Jacob US Patent 9,385,233 32 2016
  99. [PATENT] Semiconductor devices with conductive contact structures having a larger metal silicide contact area R Xie, WJ Taylor Jr, AP Jacob US Patent App. 15/065,998 6 2016
  100. [PATENT] Methods of forming a non-planar ultra-thin body semiconductor device and the resulting devices AP Jacob, R Xie, M Hargrove US Patent 9,373,721 2016
  101. [PATENT] Transistors comprising doped region-gap-doped region structures and methods of fabrication SJ Bentley, AP Jacob, CY Chen, T Yamashita US Patent 9,368,591 6 2016
  102. [PATENT] Methods of forming substrates comprised of different semiconductor materials and the resulting device BJ Pawlak, S Bentley, A Jacob US Patent 9,368,578 31 2016
  103. [PATENT] Channel cladding last process flow for forming a channel region on a FinFET device AP Jacob, WP Maszara, JA Fronheiser US Patent 9,362,405 11 2016
  104. [PATENT] FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming MH Chi, A Jacob, A Paul US Patent 9,362,277 12 2016
  105. [PATENT] Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device X Cai, R Xie, AP Jacob, WP Maszara, K Cheng, A Khakifirooz US Patent 9,349,840 2016
  106. [PATENT] Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material AP Jacob, B Doris, K Cheng, A Khakifirooz, K Rim US Patent 9,349,658 13 2016
  107. [PATENT] Fin transformation process and isolation structures facilitating different Fin isolation schemes AP Jacob, K Cheng, BB Doris, N Loubet, P Khare, R Divakaruni US Patent 9,349,730 29 2016
  108. [PATENT] Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region AP Jacob, M Hargrove, JA Fronheiser, MK Akarvardar US Patent 9,343,300 4 2016
  109. [PATENT] Self-aligned dual-height isolation for bulk FinFET MK Akarvardar, SJ Bentley, K Cheng, BB Doris, J Fronheiser, AP Jacob, ... US Patent 9,324,790 7 2016
  110. [PATENT] Fin device with blocking layer in channel region AP Jacob, MH Chi US Patent App. 14/983,329 2016
  111. [PATENT] Methods of removing fins for finfet semiconductor devices R Xie, A Knorr, AP Jacob, M Hargrove US Patent 9,318,342 12 2016
  112. [PATENT] Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices R Xie, WJ Taylor Jr, AP Jacob US Patent 9,318,552 28 2016
  113. [PATENT] Methods of forming FinFET devices with alternative channel materials AP Jacob, MK Akarvardar, M Hargrove, R Xie US Patent 9,312,387 20 2016
  114. [PATENT] Device isolation in FinFET CMOS AP Jacob, MK Akarvardar, S Bentley, T Nagumo, K Cheng, BB Doris, ... US Patent 9,305,846 1 2016
  115. [PATENT] Finfet semiconductor device with isolated channel regions AP Jacob, N Loubet US Patent App. 14/963,683 1 2016
  116. [PATENT] Semiconductor devices with replacement gate structures R Xie, X Cai, AC Wei, Q Zhang, AP Jacob, M Hargrove US Patent App. 14/963,378 1 2016
  117. [PATENT] Methods of forming semiconductor devices including an electrically-decoupled fin S Bentley, AP Jacob US Patent 9,293,324 2 2016
  118. [PATENT] Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device AP Jacob, MK Akarvardar US Patent 9,293,587 9 2016
  119. [PATENT] Method for single fin cuts using selective ion implants X Cai, AP Jacob, R Xie, B Doris, K Cheng, JR Cantone, S Mignot, ... US Patent 9,287,130 1 2016
  120. [PATENT] Methods of forming metastable replacement fins for a finfet semiconductor device by performing a replacement growth process AP Jacob, MK Akarvardar, J Fronheiser, WP Maszara US Patent App. 14/931,277 1 2016
  121. [PATENT] Methods of removing portions of at least one fin structure so as to form isolation regions when forming FinFET semiconductor devices AP Jacob US Patent 9,269,628 14 2016
  122. [PATENT] Fin device with blocking layer in channel region AP Jacob, MH Chi US Patent 9,263,587 9 2016
  123. [PATENT] Methods of forming isolated channel regions for a FinFET semiconductor device and the resulting device AP Jacob, N Loubet US Patent 9,263,580 19 2016
  124. [PATENT] Retrograde doped layer for device isolation AP Jacob, SJ Bentley, MK Akarvardar, JA Fronheiser, K Cheng, BB Doris, ... US Patent App. 14/882,308 2016
  125. [PATENT] Uniaxially-strained fd-soi finfet P Morin, M Vinet, L Grenouillet, AP Jacob US Patent 9,252,208 3 2016
  126. [PATENT] Dual-width fin structure for finfets devices MK Akarvardar, AP Jacob, A Knorr US Patent App. 14/341,423 2 2016
  127. [PATENT] Solid-state supercapacitor BS Dunn, CO Chui, AP Jacob, D Membreno, L Smith US Patent 9,245,694 10 2016
  128. [PATENT] Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a FinFET semiconductor device MK Akarvardar, JA Fronheiser, AP Jacob US Patent 9,245,980 21 2016
  129. [PATENT] Methods of forming replacement fins for a FinFET semiconductor device by performing a replacement growth process AP Jacob, MK Akarvardar, J Fronheiser, WP Maszara US Patent 9,240,342 29 2016
  130. [PATENT] Methods of forming isolated channel regions for a finfet semiconductor device and the resulting device AP Jacob, N Loubet US Patent App. 14/859,729 2 2016
  131. [PATENT] Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices R Xie, X Cai, AC Wei, Q Zhang, AP Jacob, M Hargrove US Patent 9,236,258 5 2016
  132. [PATENT] Methods of forming replacement gate structures and fins on FinFET devices and the resulting devices R Xie, AP Jacob US Patent 9,236,479 2016
  133. [PATENT] Forming alternative material fins with reduced defect density by performing an implantation/anneal defect generation process Y Qi, AP Jacob, S Liang US Patent 9,224,605 17 2015
  134. [PATENT] FinFET with insulator under channel MK Akarvardar, JA Fronheiser, AP Jacob US Patent 9,224,865 23 2015
  135. [PATENT] Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device X Cai, R Xie, AP Jacob, WP Maszara, K Cheng, A Khakifirooz US Patent 9,214,553 15 2015
  136. [PATENT] Retrograde doped layer for device isolation AP Jacob, SJ Bentley, MK Akarvardar, JA Fronheiser, K Cheng, BB Doris, ... US Patent 9,190,411 3 2015
  137. [PATENT] Semiconductor devices including an electrically-decoupled fin and methods of forming the same S Bentley, AP Jacob US Patent App. 14/274,406 5 2015
  138. [PATENT] Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices X Cai, AP Jacob, DT Pham, MV Raymond, CM Prindle, CB Labelle, ... US Patent 9,184,263 17 2015
  139. [PATENT] FinFET integrated circuits and methods for their fabrication MK Akarvardar, X Cai, AP Jacob US Patent 9,184,162 3 2015
  140. [PATENT] Methods of forming epitaxial semiconductor cladding material on fins of a FinFET semiconductor device Y Qi, AP Jacob, JA Fronheiser, MK Akarvardar, DP Brunco US Patent App. 14/267,634 11 2015
  141. [PATENT] Spin wave scattering and interference in ferromagnetic cross K Nanayakkara, AP Jacob, A Kozhanov Journal of Applied Physics 118 (16), 163904 11 2015
  142. [PATENT] Method to form defect free replacement fins by H2 anneal J Fronheiser, MK Akarvardar, AP Jacob, S Bentley US Patent 9,165,837 5 2015
  143. [PATENT] Methods of forming replacement spacer structures on semiconductor devices R Xie, X Cai, AP Jacob, A Knorr, C Prindle US Patent 9,147,748 10 2015
  144. [PATENT] Methods of forming isolated fins for a FinFET semiconductor device with alternative channel materials AP Jacob, MK Akarvardar US Patent 9,147,616 5 2015
  145. [PATENT] Methods of forming fins for FinFET semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process R Xie, A Knorr, AP Jacob, M Hargrove US Patent 9,147,730 24 2015
  146. [PATENT] Replacement fin insolation in a semiconductor device AP Jacob, MH Chi US Patent App. 14/195,884 13 2015
  147. [PATENT] Methods of forming a non-planar ultra-thin body device R Xie, AP Jacob, M Hargrove, WJ Taylor Jr US Patent App. 14/197,686 5 2015
  148. [PATENT] Methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device Y Qi, AP Jacob, S Liang US Patent 9,123,627 5 2015
  149. [PATENT] Methods of forming isolated germanium-containing fins for a FinFET semiconductor device AP Jacob, MK Akarvardar, JA Fronheiser, K Cheng, B Doris, K Rim US Patent 9,117,875 16 2015
  150. [PATENT] Methods of forming epitaxial semiconductor material on source/drain regions of a finfet semiconductor device and the resulting devices JA Fronheiser, BV Krishnan, MK Akarvardar, S Bentley, AP Jacob, J Liu US Patent App. 14/164,934 19 2015
  151. [PATENT] Process for faciltiating fin isolation schemes AP Jacob, K Cheng, BB Doris, N Loubet, P Khare, R Divakaruni US Patent 9,093,496 24 2015
  152. [PATENT] Fin pitch scaling and active layer isolation AP Jacob, MK Akarvardar, SJ Bentley, BJ Pawlak US Patent 9,076,842 7 2015
  153. [PATENT] Methods of forming replacement gate structures and fins on FinFET devices and the resulting devices R Xie, AP Jacob US Patent 9,059,042 16 2015
  154. [PATENT] Undoped epitaxial layer for junction isolation in a fin field effect transistor (finfet) device AP Jacob, MK Akarvardar US Patent App. 14/086,199 9 2015
  155. [PATENT] Methods of forming stressed multilayer FinFET devices with alternative channel materials A Paul, AP Jacob, MH Chi US Patent 9,023,705 23 2015
  156. [PATENT] Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs MK Akarvardar, AP Jacob US Patent 9,006,077 25 2015
  157. [PATENT] FinFET integrated circuits and methods for their fabrication MK Akarvardar, X Cai, AP Jacob US Patent 8,987,094 2015
  158. [PATENT] Device isolation in finFET CMOS AP Jacob, MK Akarvardar, SJ Bentley, T Nagumo, K Cheng, BB Doris, ... US Patent 8,963,259 9 2015
  159. [PATENT] Structures and methods integrating different fin device architectures AP Jacob, MK Akarvardar, MJ Hargrove US Patent App. 13/945,379 16 2015
  160. [PATENT] Group III-Sb Metamorphic Buffer on Si for p-Channel all-III-V CMOS: Electrical Properties, Growth and Surface Defects S Sasaki, S Madisetti, V Tokranov, M Yakimov, M Hirayama, S Bentley, ... MRS Online Proceedings Library Archive 1790, 13-18 2015
  161. [PATENT] Method of Device Isolation in Cladding Si through in situ doping, AP Jacob, MK Akarvardar, BB Doris, A Khakifirooz US Patent App. 13/921,265 4 2014
  162. [PATENT] Spin transistor having multiferroic gate dielectric KL Wang, A Poovannummoottil, F Xiu US Patent 8,860,006 9 2014
  163. [PATENT] Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process JA Fronheiser, JA Wahl, K Akarvardar, AP Jacob, DT Pham US Patent 8,853,019 16 2014
  164. [PATENT] Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices J Fronheiser, AP Jacob, WP Maszara, K Akarvardar US Patent App. 13/839,998 38 2014
  165. [PATENT] Integrated circuits and methods for fabricating integrated circuits with cladded non-planar transistor structures KM Akarvardar, AP Jacob US Patent 8,809,947 7 2014
  166. [PATENT] Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process BJ Pawlak, S Bentley, A Jacob US Patent 8,716,156 32 2014
  167. [PATENT] Methods of forming spin torque devices and structures formed thereby DE Nikonov, GI Bourianoff, AP Jacob US Patent 8,697,454 7 2014
  168. [PATENT] Methods of forming FinFET devices with alternative channel materials WP Maszara, AP Jacob, NV LiCausi, JA Fronheiser, K Akarvardar US Patent 8,673,718 52 2014
  169. [PATENT] Methods of forming FinFET devices with alternative channel materials WP Maszara, AP Jacob, NV LiCausi, JA Fronheiser, K Akarvardar US Patent 8,580,642 11 2013
  170. [PATENT] Methods of forming spin torque devices and structures formed thereby DE Nikonov, GI Bourianoff, AP Jacob US Patent 8,450,818 24 2013
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