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   Submission deadline
8 November 2009
13 November 2009
   Author Notification
1 December 2009
   Camera-Ready and Author Registration
20 December 2009
   Conference date
17-19 March 2010

Previous ARC workshops

ARC 2010 Program Schedule



Day 1: 17 March 2010


08:00 – 09:00


09:00 – 09:30

Introductory remarks and conference kickoff

09:30 – 10:30

Keynote 1: Ram Krishnamurthy

10:30 – 10:45

-- Break --

10:45 – 12:00

Session 1 : Architectures 1 (3 papers – 25 mins each)

12:00 – 13:00

-- Lunch --

13:00 – 14:40

Session 2 : Applications 1 (4 papers – 25 mins each)

14:40 – 15:30

Poster Session 1 (8 papers) and Refreshments

15:30 – 17:10

Session 3 : Architectures 2 (4 papers – 25 mins each)

19:00 - 22.00

Conference Dinner (Glen bar, ground floor)


Day 2: 18 March 2010


08:00 – 09:00


09:00 – 10:00

Keynote 2: Peter Y. K. Cheung

10:00 – 10:20

-- Break --

10:20 – 12:00

Session 4 : Applications 2 (4 papers – 25 mins each)

12:00 – 13:00

-- Lunch --

13:00 – 14:40

Session 5 : Design Tools 1 (4 papers – 25 mins each)

14:40 – 15:30

Poster Session 2 (7 papers) and Refreshments

15:30 – 17:10

Session 6 : Design Tools 2 (4 papers – 25 mins each)

17:30 – 21:00

Thank You Cocktail Party (Infinity 1) Thai Puppet Show (Aksara theatre)


Day 3: 19 March 2010


08:00 – 09:00


09:00 – 10:00

Keynote 3: Steven J.E. Wilton

10:00 – 11:45

Session 7 : Applications 3 (3 papers – 25 mins each)

11:45 - 12.00

Closing remarks

12:00 – 13:00

-- Lunch --

13:00 – 14:30

Altera Tutorial

14:30 – 14:45

– Break --

14:45 – 16:15

Altera Tutorial



High-performance energy-efficient reconfigurable accelerators/coprocessors

for tera-scale multi-core microprocessors

Ram Krishnamurthy


Process Variability and Degradation: New Frontier for Reconfigurable

Peter Y. K. Cheung


Towards Analytical Methods for FPGA Architecture Investigation

Steven J.E. Wilton


Session 1: Architectures - 1

Generic Systolic Array for Run-time Scalable Cores
Andrés Otero, Yana E.Krasteva, Eduardo de la Torre, Teresa Riesgo


Virtualization within a Parallel Array of Homogeneous Processing Units

Marc Stöttinger, Alexander Biedermann, Sorin A. Huss


Feasibility Study of a Self-healing Hardware Platform

Michael Reibel Boesen, Pascal Schleuniger, Jan Madsen


Session 2: Applications - 1

Application-Specific Signatures for Transactional Memory in Soft Processors

Martin Labrecque, Mark Jeffrey, J. Gregory Steffan


Towards rapid dynamic partial reconfiguration in video-based driver assistance systems
Christopher Claus, Rehan Ahmed, Florian Altenried, Walter Stechele


Parametric Encryption Hardware Design

Adrien Le Masle, Wayne Luk, Jared Eldredge, Kris Carver


A Reconfigurable Implementation of the Tate Pairing Computation over GF(2 m )*

Weibo Pan , William Marnane


Session 3: Architectures - 2

Application Specific FPGA using Heterogeneous Logic Blocks

Husain Parvez, Zied Marrakchi, Habib Mehrez


Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip

Mouna Baklouti, Philippe Marquet, Jean Luc Dekeyser, Mohamed Abid


A Dedicated Reconfigurable Architecture for Finite State Machines

Johann Glaser, Markus Damm, Jan Haase, Christoph Grimm


MEMS dynamic optically reconfigurable gate array usable under a space radiation environment

Daisaku Seto, Minoru Watanabe


Session 4: Applications – 2

An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme

Abdulhadi Shoufan


A Fused Hybrid Floating-Point and Fixed-Point Dot-product for FPGAs

Antonio Roldao Lopes, George A. Constantinides


Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods

David Boland, George A. Constantinides


Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides


Session 5: Design Tools - 1

3D Compaction: a Novel Blocking-aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices

Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev


TROUTE: A Reconfigurability-aware FPGA Router

Karel Bruneel, Dirk Stroobandt


Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing

Esam El-Araby, Vikram K. Narayana, Tarek El-Ghazawi


Routing-aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture

Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil Dutt


Session 6: Design Tools - 2

Design Automation for Reconfigurable Interconnection Networks

Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung


A Framework for Enabling Fault Tolerance in Reconfigurable Architectures

Kostas Siozios, Dimitrios Soudris, Dionisios Pnevmatikatos


QUAD - A Memory Access Pattern Analyser

S. Arash Ostadzadeh, Roel J. Meeuws, Carlo Galuzzi, Koen Bertels


Hierarchical Loop Partitioning For Rapid Generation Of Runtime Configurations

Siew-Kei Lam, Yun Deng, Jian Hu, Xilong Zhou, Thambipillai Srikanthan


Session 7: Applications - 3

Reconfigurable Computing and Task Scheduling for Active Storage Service Processing

Yu Zhang, Dan Feng


A Reconfigurable Disparity Engine for Stereovision in Advanced Driver

Assistance Systems

Mehdi Darouich, Stephane Guyetant, Dominique Lavenier


A Modified Merging Approach for Datapath Configuration Time Reduction

Mahmood Fazlali, Ali Zakerolhosseini, Georgi Gaydadjiev


Poster Session 1

Reconfigurable Computing Education in Computer Science

Abdulhadi Shoufan, Sorin Alexander Huss


Hardware implementation of the orbital function for quantum chemistry calculations

Maciej Wielgosz, Ernest Jamro, Pawel Russek, Kazimierz Wiatr


Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing

Suhaib A. Fahmy, Linda Doyle


Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures

Kunjan Patel, C. J. Bleakley


A GMM-based Speaker Identi_cation System on FPGA

Phak Len Eh Kan, Tim Allen, Steven F. Quigley


An FPGA-based Real-Time Event Sampler

Niels Penneman, Luc Perneel, Martin Timmerman, Bjorn De Sutter


A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster

Masato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer


An Analysis of Delay Based PUF Implementations on FPGA

Sergey Morozov, Abhranil Maiti, Patrick Schaumont


Poster Session 2

Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor

Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka


FPGA Implementation of QR Decomposition Using MGS Algorithm

Akkarat Boonpoonga, Sompop Janyavilas, Phaophak Sirisuk, Monai Krairiksh


Memory-Centric Communication Architecture for Reconfigurable Computing

Kyungwook Chang, Kiyoung Choi


Integrated Design Environment for Reconfigurable HPC

Lilian Janin, Shoujie Li, Doug Edwards


Architecture-Aware Custom Instruction Generation for Reconfigurable Processors

Alok Prakash, Siew-Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan


Cost and Performance Evaluation of a Noise Filter for Partitioning in Co-design Methodologies

Victoria Rodellar, Elvira Martínez de Icaya, Francisco Díaz, Virginia Peinado


Towards a Tighter Integration of Generated and Custom-Made Hardware

Harald Devos, Wim Meeus, Dirk Stroobandt


Pipelined Microprocessors Optimization and Debugging

Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita


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