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Dates
   Submission deadline
8 November 2009
13 November 2009
   Author Notification
1 December 2009
   Camera-Ready and Author Registration
20 December 2009
   Conference date
17-19 March 2010

 

Keynote Speakers

 

Title: "Process Variability and Degradation: New Frontier for Reconfigurable"

Prof. Peter Y K Cheung

Progress in VLSI technology is driven by increasing circuit density through process scaling, but with shrinking geometry comes an increasing threat to reliability. FPGAs are uniquely placed to tackle degradation and faults due to their regular structure and ability to reconfigure, giving them the potential to implement system-level reliability enhancements. In this keynote, the problems relating to increasing process variations will be explored. The possible role that FPGA may play in alleviating such process variability effects will be discussed. Even more challenging is the problem of degradations in very small geometry devices resulting in increase delays and eventual failures in FPGAs. New ideas in exploiting reconfigurability to handle both variability and degradation presents no opportunities for FPGAs.

 

Prof. Cheung is a professor of Digital Systems and Head of the Department of Electrical & Electronic Engineering, Imperial College London. His research interests include: Field Programmable Gate Arrays (FPGA) and Reconfigurable Computing; Analogue and Digital CAD tools, in particular high level synthesis and hardware/software codesign; Low power and high performance IC architectures for signal and image processing; and Mixed signal IC designs.

 

 

Title: "High-performance energy-efficient reconfigurable accelerators/co-processors for tera-scale multi-core microprocessors"

Ram Krishnamurthy

With the emergence of high-performance multi-core microprocessors in the sub-45nm technology era, specialized hardware accelerator engines embedded within the core architecture have the potential to achieve 10-100X increase in energy efficiency across a wide domain of compute-intensive signal processing and scientific algorithms. In this talk, we present multi-core microprocessors integrated with on-die energy-efficient reconfigurable accelerator and co-processor engines to achieve well beyond tera-scale performance in sub-45nm technologies. Recent trends and advances in multi-core microprocessors will be presented, followed by key enablers for reconfigurability of specialized hardware engines to support multiple protocols while substantially improving time-to-market and amortizing die area cost across a wide range of compute workloads and functions. Specific design examples and case studies supported by silicon measurements will be presented to demonstrate reconfigurable engines for wireless baseband, signal processing and graphics/media applications. Power efficient optimization of reconfigurable processors to support fine-grain power management, dynamic on-the-fly configurability and standby-mode leakage reduction and low-voltage operability will also be described.

 

Ram K. Krishnamurthy is a Senior Principal Engineer with the Circuits and Systems Research Labs, Intel Corporation, Hillsboro , OR , where he heads the high-performance and low-voltage research group. He received the B.E. degree in Electrical Engineering from Regional Engineering College , Trichy , India , in 1993, and the Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University , Pittsburgh , PA , in 1998. He has been with Intel Corporation since 1998. He holds 80 issued patents and has published over 75 conference/journal papers and 2 book chapters on high-performance energy-efficient microprocessor design. He serves as Intel´s representative on the SRC Design Sciences Task Force and on the program committees of the ISSCC, CICC, and SOCC conferences. He served as the Technical Program Chair/General Chair for the 2005/2006 IEEE International Systems-on-Chip Conference. He has received the 2002 Outstanding Industry Mentor Award from SRC, Intel Awards for most patents filed in 2001 and most patents issued in 2003, and the MIT Technology Review´s TR35 Innovator Award in 2006. He has received two Intel Achievement Awards, in 2004 and 2008, for the development and technology transfer of novel high-performance execution core arithmetic circuits and special-purpose hardware encryption accelerators. His research interests are in high-performance/low-power data-path and DSP, reconfigurable architectures and design, and on-die interconnect design. He is a Senior Member of IEEE.

 

 

Title: "Towards Analytical Methods for FPGA Architecture Investigation"

Prof. Steven J.E. Wilton

In the past 20 years, the capacity of FPGAs has grown by 200x and the speed has increased by 40x. Much of this dramatic improvement has been the result of architectural improvements. FPGA architectural enhancements are often developed in a somewhat ad-hoc manner. Expert FPGA architects perform experiments in which benchmark circuits are mapped using representative computer-aided design (CAD) tools, and the resulting density, speed, and/or power are estimated. Based on the results of these experiments, architects use their intuition and experience to design new architectures, and then evaluate these architectures using another set of experiments. This is repeated numerous times, until a suitable architecture is found.

During this process, there is virtually no body of theory that architects can use to speed up their investigations. Such insight, however, would be extremely valuable. A better understanding of the tradeoff between flexibility and efficiency may allow FPGA architects to uncover improved architectures quickly. Although it is unlikely that such an understanding would immediately lead to an optimum architecture, it may provide the means to "bound" the search space so that a wider variety of "interesting" architectures can be experimentally evaluated.

In this talk, I will describe recent work towards the development of such a theory. The current approach is to supplement the experimental methodology with a set of analytical expressions that relate architectural parameters to the area, speed, and power dissipation of an FPGA. Optimizing these analytical expressions is done using techniques such as geometric programming. I will summarize current research in this area, as well as try to provide some insight into how far we can go with these techniques.

 

[Steve Wilton]

Steven J.E. Wilton received his M.A.Sc. and Ph.D. degrees in Electrical and Computer Engineering from the University of Toronto in 1992 and 1997 respectively. In 1997, he joined the Department of Electrical and Computer Engineering at the University of British Columbia , where he is now a Professor and Associate Head Academic. During 2003 and 2004, Dr. Wilton was a Visiting Professor in the Department of Computing at Imperial College , London , U.K, and at the Interuniversity MicroElectronics Center (IMEC) in Leuven , Belgium . He has served as a consultant for Cypress Semiconductor and Altera Corporation and is the Chief Research Officer and co-founder of Veridae Systems. His research focuses on SoCs and FPGAs, and the CAD tools that target these devices.

In 2005, he was the Program Chair for the ACM International Symposium on Field-Programmable Gate Arrays and the program co-chair for the International Conference on Field Programmable Logic and Applications. In 2008, he was the program co-chair for the International Conference on Application-Specific Systems, Architecture, and Processors. He is on the steering committee for the ACM International Symposium on Field-Programmable Gate Arrays and the International Conference on Field-Programmable Technology (FPT). He is currently an Associate Editor of the ACM Transactions on Reconfigurable Technology and Systems.

He received best paper awards at the International Conference on Field-Programmable Technology in 2003, 2005, and 2007 and at the International Conference on Field-Programmable Logic and Applications in 2001 , 2004, 2007, and 2008. In 1998, he won the Douglas Colton Medal for Research Excellence for his research into FPGA memory architectures.

 



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