With the increasing number of available transistors on a die it is now
possible to integrate on a single die various computing elements interconnected
via reconfigurable networks in what is commonly designated as Systems-On-A-Chip (SOC).
The computing elements of the system can incorporate reconfigurable techniques
to allow them to be tuned to application-specific functions.
This project focuses on system-level mapping of applications written in
imperative programming languages such as C to System-On-A-Chip systems
implemented using multiple Field-Programmable Gate Arrays (FPGAs) architectures.
The proposed research addresses system-level partitioning and scheduling of the
execution of tasks among computing cores based on high-level program analysis as
well as managing the storage and movement of data between both internal and
external memories and between tasks.
The proposed research addresses these issues by the synergistic collaboration of
program analysis, parallelizing compiler technology and behavioral synthesis tools.
This project is the first comprehensive, and automatic, integration of
parallelizing compiler technology with EDA synthesis. It is also the
first attempt to integrate in a compiler high-level loop transformations
guided by estimates provided by commercially available synthesis tools.
The end result is a realistic and accurate design space exploration strategy
we believe is widely applicable to current and future multiple FPGA systems
as well as future System-On-a-Chip (SoC) systems.
An automated application mapping approach that addresses system-level issues
as proposed in this research will ultimately allow designers to explore a wider
range of application mapping strategies for SoC systems.