Disruptive Electronics


Active Projects


Radiation Effects on Electronics in Aligned Carbon Nanotube Technology (RadCNT)

Sponsor - DTRA (Basic Science Program)

The RadCNT Program aims at developing fundamental understanding of radiation effects on carbon nanotube (CNT) and graphene based transistors.  Effects studied include charge generation, recombination, drift/diffusion, charge sharing, and charge collection.  A key aspect of this Program is an experimental radiation testing effort looking at total dose and single event upset effects in carbon based transistors.  This experimental effort is augmented by analytical modeling of radiation induced effects including oxide charge trapping, single-event charge generation, and displacement damage.  We are beginning with single transistor devices and then expanding our radiation effects analysis to basic circuits comprised of carbon-based transistors.

Techniques for Estimating Reliability in COTS ICs (TERCI)

Sponsor - DARPA (IRIS Program)

TERCI focuses on developing the technology to predict the long-term reliability of COTS ICs (both Digital and Analog Mixed Signal) from a very limited sample set (≤ 10 chips).  We focus on wear-out or “aging” related reliability effects including negative-bias-temperature-instability (NBTI), time-dependent-dielectric-breakdown (TDDB), and hot carrier (HC).  A three-prong approach is used in our prediction methodology:  1) building better wear-out models for select CMOS technologies using experimental reliability data, 2) building custom reliability circuit simulation tools to apply these models to IC test articles, 3) Developing “in-situ” testing methods to acquire reliability data from COTs ICs (without the use of custom reliability test circuits).  The ultimate goal is the development of efficient methods for evaluating mean-time-to-failure of COTs ICs from very limited sample sets.

Modeling and Simulation of Error Code-based SEU Radiation-Hardening for Computational and Boolean Logic Elements (CORRECT)

Sponsor - DTRA (CORRECT Program)

Block-code-based error detection and correction techniques (e.g., Hamming, Reid-Solomon codes), and circuit-based radiation-hardening methods (e.g. Dual Interlocked Cells) have been shown to effectively mitigate Single-Event-Upsets in memory elements (SRAMs, registers, etc.). However, an efficient implementation of SEU mitigation techniques in the processing components of a computing chain has yet remained elusive. Typical methods employed today include triple modular redundancy (TMR) which come with high area and power penalties. This project focuses on exploring a novel radiation-hardening approach to specifically tackle the issue of SEU occurrences in computational and Boolean logic, by embedding residue arithmetic coding (RAC) into the computational processing chain, and linear block-coding in the Boolean processing logic.  The algorithms proposed are highly flexible, can be applied to any computational or Boolean logic block, and require no a- priori assumption on the location of errors in the processing chain. Most importantly, they can be seamlessly integrated into the computing and processing constructs with very low overhead burden on the underlying operations.  The ultimate goal of this effort is the development of radiation hardening approaches for logic operations with good radiation performance together with low overheads in terms of area and power.

Trusted Integrated Circuits (TIC)

Sponsor - IARPA (TIC Program)

The goal of this project is the assured and trusted availability of state of the art CMOS from overseas untrusted foundries.  To this end, a “split-fabrication” paradigm is explored in which front-end-of-the-line (FEOL) active transistor layers are fabricated in an overseas untrusted foundry and back-end-of-the-line (BEOL) passive interconnect layers are fabricated in an on-shore trusted foundry.   To assure the security and trust of this approach, the “split-fab” process is combined with deliberate design obfuscation such that design intent cannot be derived from FEOL data only.  We are playing a supporting role in this Program with responsibilities including commercial Fab coordination, design flow development, testing & evaluation and Performer progress reviews.

Power Efficiency Revolution For Embedded Computing Technologies (PERFECT)

Sponsor – DARPA

This program seeks breakthrough advances in power efficient embedded computing.  Current embedded computing systems have power efficiencies around 1 Gigaflops per Watt (1 GOPS/W).  The PERFECT program seeks innovative solutions to increase this efficiency to the range of 75 GOPs/W.  Our approach is based on a novel field-programmable-gate-array FPGA concept.  We develop an innovative ultra low power FPGA fabric based on near/sub-threshold interconnect approaches combined with a 3DIC-based architecture.  Key functions are partitioned into multiple active tiers with the objective of maximizing power efficiency and regaining performance lost in low voltage operation regimes.