Passcode: 862998

Hardware verification remains one of the most complex, time-consuming, and resource-intensive stages of modern chip development. As designs grow exponentially in scale and complexity, traditional automation techniques are no longer sufficient to meet aggressive schedules and coverage goals. Recent advances in generative AI and foundation models are enabling a fundamental shift—from rule-based automation toward intelligent, autonomous verification systems. This talk explores how AI is transforming hardware verification across the entire workflow, including specification understanding, test plan generation, assertion creation, testbench development, debug, and coverage closure. We will discuss how large language models can reason about hardware intent, generate verification collateral, and assist engineers in identifying gaps, inconsistencies, and corner cases earlier in the design cycle. Beyond productivity improvements, we will examine the emerging transition from AI as a passive assistant (“copilot”) to an active participant capable of driving verification tasks autonomously. The presentation will highlight practical deployment considerations, real-world results, integration with existing EDA flows, and lessons learned from applying AI to production-scale semiconductor projects. Finally, we will discuss the path forward toward AI-native verification environments and how autonomous systems will reshape engineering workflows, improve design quality, and accelerate time-to-silicon.