Next-generation space missions are continually driving on-board science data processing requirements through continuous observations, higher instrument fidelity, low-latency look ahead products, autonomous science and health operation, and multi-satellite or constellation collaboration. Heterogeneous on board processing has been recognized as a viable path towards achieving higher processing rates within a size, weight, power and radiation tolerance envelope, however this has led to an architecture trade space that can no longer be manually analyzed.
The goal of the On-board Computing Analysis Framework is to replace the manual, waterfall development process of board design, and it replace it with a tool-enabled, iterative feedback approach, capable of exploring the trade space of heterogeneous architectures. Using this framework, a designer can rapidly define different architectures using ArchGen. This board model is then used to generate the heterogenous compiler environment and the corresponding simulators and/or emulators in order to effectively model the end performance of the system on a given application.
The framework supports Multi-core CPUs (ARM and PowerPC), FPGAs, DSPs, and GPUs. A benchmark of applications can then be used to scientifically compare and explore candidate architectures. The framework can be installed locally, or can be utilized in the AWS cloud, where we are research FPGA emulation on the F-1 instances. The cloud environment also enables multiple instances to be spawned in order to represent and experiment with constellations.
