Patents
2022
"Multimode waveguide bends with features to reduce bending loss" US PATENT 1127520, Yusheng Bian, Ajey Poovannummoottil Jacob [link]
"Optical power splitters including a non-linear waveguide taper" US PATENT 11256030, Sujith Chandran, Yusheng Bian, Jaime Viegas, Ajey Poovannummoottil Jacob [link]
"Photonic transmitter drivers with logic using cascaded differential transistor pairs stepped by supply voltage differences" US PATENT 11239633, Jacob Ajey Poovannummoottil, Serunjogi Solomon M, Sanduleanu Mihai Adrian Tiberiu [link]
"Integrated circuits with embedded memory structures and methods for fabricating the same" US PATENT 11233191, Jacob Ajey P, Ramanathan Eswar [link]
"Multifunctional metamaterial-based optical device" US PATENT 11227960, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Image sensor incorporating an array of optically switchable magnetic tunnel junctions" US PATENT 11226231, Jaiswal Akhilesh R, Jacob Ajey Poovannummoottil, Bian Yusheng, Pritchard David C [link]
"Polarization switches including a phase change material" US PATENT 11221506, Shank Steven M, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Image sensor incorporating an array of optically switchable magnetic tunnel junctions" US PATENT 11226231, Jaiswal Akhilesh R, Jacob Ajey Poovannummoottil, Bian Yusheng, Pritchard David C [link]
2021
"Integrated pixel and two-terminal non-volatile memory cell and an array of cells for deep in-sensor, in-memory computing" US PATENT 11195580, Jaiswal Akhilesh, Jacob Ajey Poovannummoottil [link]
"Fin-based photodetector structure" US PATENT 11177404, Jacob Ajey Poovannummoottil, Bian Yusheng, Shank Steven [link]
"Waveguide structures" US PATENT 11163114, Bian Yusheng, Jacob Ajey Poovannummoottil, Shank Steven M [link]
"Optical couplers with non-linear tapering" US PATENT 11150407, Bian Yusheng, Jacob Ajey Poovannummoottil, Chandran Sujith [link]
"Circuit structure and method for memory storage with memory cell and MRAM stack" US PATENT 11145348, Jaiswal Akhilesh R, Jacob Ajey Poovannummoottil, Soss Steven R [link]
"Polarizers with an absorber" US PATENT 11137543, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Reconfigurable optical antenna coupler" US PATENT 11126019, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Polarizer with multiple evanescently coupled waveguides" US PATENT 11125944, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Polarizers including stacked elements" US PATENT 11105978, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Inter-chip and intra-chip communications" US PATENT 11092872, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Waveguide absorbers" US PATENT 11092743, Bian Yusheng, Jacob Ajey Poovannummoottil, Lee Won Suk [link]
"Laser with a gain medium layer doped with a rare earth metal with upper and lower light-confining features" US PATENT 11088503, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Sensing scheme for STT-MRAM using low-barrier nanomagnets" US PATENT 11087814, Agrawal Amogh, Jacob Ajey Poovannummoottil, Paul Bipul C [link]
"Waveguide absorbers" US PATENT 11079544, Bian Yusheng, Peng Bo, Rakowski Michal, Jacob Ajey Poovannummoottil [link]
"Integrated pixel and three-terminal non-volatile memory cell and an array of cells for deep in-sensor, in-memory computing" US PATENT 11069402, Jaiswal Akhilesh, Jacob Ajey Poovannummoottil [link]
"Trench-based optical components for photonics chips" US PATENT 11067751, Meagher Colleen, Nummy Karen, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Waveguides with cladding layers of gradated refractive index" US PATENT 11067749, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Waveguide structures" US PATENT 11061186, Jacob Ajey Poovannummoottil, Dahlem Marcus V S, Zafar Humaira, Khilo Anatol, Chandran Sujith [link]
"Non-volatile memory element arrays in a wheatstone bridge arrangement" US PATENT 11056535, Jacob Ajey Poovannummoottil, Agrawal Amogh [link]
"Waveguide couplers providing conversion between waveguides" US PATENT 11036003, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Micro-ring modulator" US PATENT 11029465, Rakowski Michal, Bian Yusheng, Jacob Ajey Poovannummoottil, Shank Steven M [link]
"Non-planar grating couplers for antennas" US PATENT 11002916, Bian Yusheng, Jacob Ajey Poovannummoottil, Rakowski Michal, Peng Bo [link]
"Apparatus and method for in-memory binary convolution for accelerating deep binary neural networks based on a non-volatile memory structure" US PATENT 10997498, Agrawal Amogh, Jacob Ajey Poovannummoottil [link]
"Switchable polarization splitters" US PATENT 10996398, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Non-planar waveguide structures" US PATENT 10989877, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Optical fiber coupler having hybrid tapered waveguide segments and metamaterial segments" US PATENT 10989876, Peng Bo, Jacob Ajey Poovannummoottil, Bian Yusheng [link]
"Waveguide crossings having arms shaped with a non-linear curvature" US PATENT 10989873, Jacob Ajey Poovannummoottil, Bian Yusheng, Chandran Sujith, Dahlem Marcus [link]
"Waveguide bends with mode confinement" US PATENT 10989872, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"MRAM device comprising random access memory (RAM) and embedded read only memory (ROM)" US PATENT 10964367, Jaiswal Akhilesh, Jacob Ajey Poovannummoottil, Soss Steven [link]
"Optical fiber coupler structure having manufacturing variation-sensitive transmission blocking region" US PATENT 10955614, Peng Bo, Jacob Ajey Poovannummoottil, Bian Yusheng [link]
"Hybrid wavelength-division multiplexing filters" US PATENT 10942321, Chandran Sujith, Dahlem Marcus, Jacob Ajey Poovannummoottil, Bian Yusheng, Paredes Bruna, Viegas Jaime [link]
"Grating couplers with a silicide mirror" US PATENT 10921526, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Semiconductor detectors with butt-end coupled waveguide and method of forming the same" US PATENT 10910503, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Switchable and reconfigurable grating couplers" US PATENT 10895689, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
2020
"Transverse-electric (TE) pass polarizer" US PATENT 10871614, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Semiconductor detectors integrated with Bragg reflectors" US PATENT 10818807, Jacob Ajey Poovannummoottil, Letavic Theodore J, Thomas Abu, Bian Yusheng [link]
"Tunable grating couplers" US PATENT 10816872, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Polarizers with confinement cladding" US PATENT 10816728, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Multimode waveguide bends with features to reduce bending loss" US PATENT 10816727, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Edge couplers for photonics applications" US PATENT 10816726, Peng Bo, Bian Yusheng, Jacob Ajey Poovannummoottil, Houghton Thomas, Sahin Asli [link]
"Waveguide intersections incorporating a waveguide crossing" US PATENT 10816725, Bian Yusheng, Jacob Ajey Poovannummoottil, Thomas Abu [link]
"Integrated graphene detectors with waveguides" US PATENT 10804416, Jacob Ajey P [link]
"Heterogeneous directional couplers for photonics chips" US PATENT 10795083, Bian Yusheng, Jacob Ajey Poovannummoottil, Shank Steven M [link]
"Bragg gratings with airgap cladding" US PATENT 10795082, Jacob Ajey Poovannummoottil, Bian Yusheng, Letavic Theodore, Giewont Kenneth J, Shank Steven M [link]
"FinFET with multilayer fins for multi-value logic (MVL) applications" US PATENT 10756213, Chi Minhwa, Jacob Ajey, Paul Abhijeet [link]
"Backup and/or restore of a memory circuit" US PATENT 10854291, Jaiswal Akhilesh Ramlaut, Bhargava Mudit, Lattimore George McNeil [link]
"Read and logic operation methods for voltage-divider bit-cell memory devices" US PATENT 10783957, Jaiswal Akhilesh Ramlaut, Bhargava Mudit [link]
"MRAM read and write methods using an incubation delay interval" US PATENT 10593397, Jaiswal Akhilesh Ramlaut, Bhargava Mudit [link]
"Electro-optic modulators with stacked layers" US PATENT 10747030, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Silicon nitride grating couplers" US PATENT 10746925, Jacob Ajey P, Bian Yusheng [link]
"Stacked waveguide arrangements providing field confinement" US PATENT 10746921, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Grating couplers with cladding layer(s)" US PATENT 10746907, Jacob Ajey Poovannummoottil, Bian Yusheng [link]
"Resistive nonvolatile memory structure employing a statistical sensing scheme and method" US PATENT 10726896, Jacob Ajey Poovannummoottil, Agrawal Amogh [link]
"Waveguide crossings with a non-contacting arrangement" US PATENT 10718903, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Multiple-layer arrangements including one or more dielectric layers over a waveguide" US PATENT 10698159, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Three dimensional optical interconnects" US PATENT 10690845, Jacob Ajey Poovannummoottil, Thomas Abu, Bian Yusheng [link]
"Vertical nanowires formed on upper fin surface" US PATENT 10685847, Bentley Steven, Farrell Richard A, Schmid Gerard, Jacob Ajey Poovannummoottil [link]
"Electro-optic modulators with layered arrangements" US PATENT 10684530, Bian Yusheng, Jacob Ajey Poovannummoottil, Thomas Abu [link]
"Neuromorphic memory device" US PATENT 10672465, Agrawal Amogh, Jacob Ajey Poovannummoottil [link]
"Composite waveguiding structures including semiconductor fins" US PATENT 10670804, Bian Yusheng, Thomas Abu, Jacob Ajey Poovannummoottil [link]
"Resistive nonvolatile memory cells with shared access transistors" US PATENT 10665281, Jacob Ajey Poovannummoottil, Agrawal Amogh, Paul Bipul C [link]
"Electro-optic modulators with stacked metal, dielectric, and active layers" US PATENT 10649245, Bian Yusheng, Jacob Ajey Poovannummoottil, Thomas Abu [link]
"Back-end-of-line blocking structures arranged over a waveguide core" US PATENT 10649140, Bian Yusheng, Jacob Ajey Poovannummoottil, Thomas Abu [link]
"Polarizers and polarization splitters phase-matched with a back-end-of-line layer" US PATENT 10641956, Bian Yusheng, Jacob Ajey Poovannummoottil, Thomas Abu [link]
"Multiple-layer arrangements using tunable materials to provide switchable optical components" US PATENT 10585245, Bian Yusheng, Thomas Abu, Jacob Ajey Poovannummoottil [link]
"Grating couplers with multiple configurations" US PATENT 10585219, Jacob Ajey Poovannummoottil, Bian Yusheng [link]
"Slot assisted grating based transverse magnetic (TM) transmission mode pass polarizer" US PATENT 10557989, Jacob Ajey Poovannummoottil, Dahlem Marcus V S, Zafar Humaira, Khilo Anatol, Chandran Sujith [link]
2019
"Magneto-resistive memory structures with improved sensing, and associated sensing methods" US PATENT 10515679, Jaiswal Akhilesh, Jacob Ajey P, Paul Bipul C, Taylor William, Shum Danny PakChum [link]
"Integrated circuits having memory cells with shared bit lines and shared source lines" US PATENT 10510392, Paul Bipul C, Jaiswal Akhilesh, Jacob Ajey Poovannummoottil, Taylor William, Shum Danny PakChum [link]
"Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for differential bit operation and methods for fabricating the same" US PATENT 10468456, Jacob Ajey Poovannummoottil, Akhilesh Jaiswal [link]
"Logic-in-memory computations for non-volatile resistive random access memory (RAM) array" US PATENT 10468084, Jaiswal Akhilesh R, Jacob Ajey Poovannummoottil [link]
"Integrated circuits with look up tables, and methods of producing and operating the same" US PATENT 10468083, Jaiswal Akhilesh, Jacob Ajey Poovannummoottil [link]
"Methods, apparatus, and manufacturing system for forming source and drain regions in a vertical field effect transistor" US PATENT 10461173, Jacob Ajey Poovannummoottil, Tran Xuan Anh, Zang Hui, Haran Bala, Kalaga Suryanarayana [link]
"Stacked elongated nanoshapes of different semiconductor materials and structures that incorporate the nanoshapes" US PATENT 10453750, Pawlak Bartlomiej J, Bouche Guillaume, Jacob Ajey P [link]
"Waveguides including a patterned dielectric layer" US PATENT 10444433, Bian Yusheng, Thomas Abu, Jacob Ajey Poovannummoottil, Giewont Kenneth J, Nummy Karen, Stricker Andreas, Peng Bo [link]
"Waveguide bends with field confinement" US PATENT 10436982, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Waveguide-to-waveguide couplers with multiple tapers" US PATENT 10429582, Bian Yusheng, Jacob Ajey Poovannummoottil, Shank Steven M [link]
"Polarization splitters based on stacked waveguides" US PATENT 10429581, Thomas Abu, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
"Integrated circuits including magnetic random access memory structures and methods for fabricating the same" US PATENT 10411069, Jacob Ajey Poovannummoottil, Akhilesh Jaiswal [link]
"FinFETs for light emitting diode displays" US PATENT 10396121, Jacob Ajey P, Banna Srinivasa, Nayak Deepak [link]
"FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming" US PATENT 10388790, Chi Minhwa, Jacob Ajey, Paul Abhijeet [link]
"Light emitting diodes (LEDs) with stacked multi-color pixels for displays" US PATENT 10388691, Banna Srinivasa, Nayak Deepak, Jacob Ajey P [link]
"Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for dual bit operation and methods for fabricating the same" US PATENT 10381406, Jacob Ajey Poovannummoottil, Akhilesh Jaiswal [link]
"Integrated graphene detectors with waveguides" US PATENT 10374106, Jacob Ajey P [link]
"Integrated vertical transistors and light emitting diodes" US PATENT 10355043, Jacob Ajey P, Nayak Deepak K, Banna Srinivasa R [link]
"Graphene contacts on source/drain regions of FinFET devices" US PATENT 10325812, Jacob Ajey Poovannummoottil [link]
"Heterogeneous integration of 3D SI and III-V vertical nanowire structures for mixed signal circuits fabrication" US PATENT 10319642, Patil Suraj Kumar, Jacob Ajey P [link]
"Light emitting diodes (LEDs) with integrated CMOS circuits" US PATENT 10283560, Nayak Deepak, Banna Srinivasa, Jacob Ajey P [link]
"Light emitting diodes" US PATENT 10263151, Jacob Ajey P, Banna Srinivasa, Nayak Deepak [link]
"Grating couplers with multiple configurations" US PATENT 10241269, Jacob Ajey Poovannummoottil, Bian Yusheng [link]
"Light emitting diode structures" US PATENT 10217900, Nayak Deepak K, Banna Srinivasa R, Jacob Ajey P [link]
"Vertical field effect transistor formation with critical dimension control" US PATENT 10217846, Xie Ruilong, Bentley Steven, Sung Min Gyu, Park Chanro, Soss Steven, Zang Hui, Wu Xusheng, Qi Yi, Jacob Ajey P, Akarvardar Murat K, Adusumilli Siva P, Shu Jiehui, Huang Haigou, Zhang John H [link]
"LEDs with three color RGB pixels for displays" US PATENT 10199429, Banna Srinivasa, Nayak Deepak, Jacob Ajey P [link]
"Multiple directed self-assembly material mask patterning for forming vertical nanowires" US PATENT 10186577, Bentley Steven, Farrell Richard A, Schmid Gerard, Jacob Ajey Poovannummoottil [link]
"Hybrid grating couplers that overlap via an interconnect structure having a metallization layer" US PATENT 10185092, Bian Yusheng, Jacob Ajey Poovannummoottil [link]
2018
"Methods of forming a vertical transistor device with a channel structure comprised of alternative semiconductor materials" US PATENT 10090385, Jacob Ajey Poovannummoottil [link]
"Semiconductor wafers with reduced bow and warpage" US PATENT 10056453, Jacob Ajey Poovannummoottil, Banna Srinivasa R, Nayak Deepak K, Pawlak Bartlomiej J [link]
"Programmable via devices with metal/semiconductor via links and fabrication methods thereof" US PATENT 10056331, Jacob Ajey P, Patil Suraj K, Chi Minhwa [link]
"Methods of forming NMOS and PMOS finFET devices and the resulting product" US PATENT 10056300, Jacob Ajey Poovannummoottil [link]
"Integrated display system with multi-color light emitting diodes (LEDs)" US PATENT 10037981, Banna Srinivasa, Jha Sanjay, Nayak Deepak, Jacob Ajey P [link]
"Methods of forming fin isolation regions under tensile-strained fins on FinFET semiconductor devices" US PATENT 10026659, Jacob Ajey Poovannummoottil, Akarvardar Murat Kerem, Fronheiser Jody A [link]
"Methods of forming graphene contacts on source/drain regions of FinFET devices" US PATENT 9972537, Jacob Ajey Poovannummoottil [link]
"Common fabrication of multiple FinFETs with different channel heights" US PATENT 9960257, Akarvardar Murat Kerem, Fronheiser Jody A, Jacob Ajey Poovannummoottil [link]
"Multiwidth finFET with channel cladding" US PATENT 9954104, Xie Ruilong, Jacob Ajey Poovannummoottil [link]
"Method for forming nanowires including multiple integrated devices with alternate channel materials" US PATENT 9953882, Jacob Ajey P [link]
"LEDs with three color RGB pixels for displays" US PATENT 9941330, Banna Srinivasa, Nayak Deepak, Jacob Ajey P [link]
"Light emitting diodes (LEDs) with integrated CMOS circuits" US PATENT 9941329, Nayak Deepak, Banna Srinivasa, Jacob Ajey P [link]
"Directed self-assembly material etch mask for forming vertical nanowires" US PATENT 9865682, Bentley Steven, Farrell Richard A, Schmid Gerard, Jacob Ajey Poovannummoottil [link]
"Non-planar monolithic hybrid optoelectronic structures and methods" US PATENT 9864136, Jacob Ajey P [link]
"Silicon waveguide devices in integrated photonics" US PATENT 9864132, Augur Roderick A, Jacob Ajey Poovannummoottil, Shank Steven M [link]
2017
"Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide" US PATENT 9842897, Akarvardar Murat K, Jacob Ajey P [link]
"Method for forming nanowires including multiple integrated devices with alternate channel materials" US PATENT 9831131, Jacob Ajey P [link]
"Methods of forming NMOS and PMOS FinFET devices and the resulting product" US PATENT 9824935, Jacob Ajey Poovannummoottil [link]
"Programmable via devices with metal/semiconductor via links and fabrication methods thereof" US PATENT 9812393, Jacob Ajey P, Patil Suraj K, Chi Minhwa [link]
"Methods of forming PMOS and NMOS FinFET devices on CMOS based integrated circuit products" US PATENT 9799767, Jacob Ajey Poovannummoottil [link]
"Semiconductor structure with anti-efuse device" US PATENT 9754903, Patil Suraj K, Chi Minhwa, Jacob Ajey Poovannummoottil [link]
"Heterogeneous integration of 3D Si and III-V vertical nanowire structures for mixed signal circuits fabrication" US PATENT 9754843, Patil Suraj Kumar, Jacob Ajey P [link]
"Methods of forming PMOS FinFET devices and multiple NMOS FinFET devices with different performance characteristics" US PATENT 9748387, Jacob Ajey Poovannummoottil [link]
"Methods of forming NMOS and PMOS FinFET devices and the resulting product" US PATENT 9741622, Jacob Ajey Poovannummoottil [link]
"Electrical isolation of FinFET active region by selective oxidation of sacrificial layer" US PATENT 9716174, Akarvardar Murat Kerem, Fronheiser Jody A, Jacob Ajey Poovannummoottil [link]
"Directed self-assembly material growth mask for forming vertical nanowires" US PATENT 9698025, Bentley Steven, Farrell Richard A, Schmid Gerard, Jacob Ajey Poovannummoottil [link]
"Programmable devices with current-facilitated migration and fabrication methods" US PATENT 9691497, Patil Suraj K, Chi Minhwa, Jacob Ajey P [link]
"Fin isolation structures facilitating different fin isolation schemes" US PATENT 9673222, Jacob Ajey Poovannummoottil, Cheng Kangguo, Doris Bruce, Loubet Nicolas, Khare Prasanna, Divakaruni Rama [link]
"Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material" US PATENT 9673083, Jacob Ajey Poovannummoottil, Doris Bruce, Cheng Kangguo, Khakifirooz Ali, Rim Kern [link]
"FinFET device including a dielectrically isolated silicon alloy fin" US PATENT 9634123, Jacob Ajey Poovannummoottil [link]
"Folded ballistic conductor interconnect line" US PATENT 9633947, Jacob Ajey Poovannummoottil [link]
"Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device" US PATENT 9627245, Jacob Ajey Poovannummoottil, Doris Bruce, Cheng Kangguo, Loubet Nicolas [link]
"Methods of forming low defect replacement fins for a FinFET semiconductor device and the resulting devices" US PATENT 9614058, Fronheiser Jody, Jacob Ajey P, Maszara Witold P, Akarvardar Kerem [link]
"Methods of forming fins for a FinFET device by forming and replacing sacrificial fin structures with alternative materials" US PATENT 9590040, Akarvardar Murat Kerem, Jacob Ajey Poovannummoottil [link]
"Methods of modulating strain in PFET and NFET FinFET semiconductor devices" US PATENT 9589849, Jacob Ajey Poovannummoottil, Akarvardar Murat Kerem, Doris Bruce, Khakifirooz Ali [link]
"Solid-state supercapacitor" US PATENT 9570244, Dunn Bruce S, Chui Chi On, Jacob Ajey Poovannummoottil, Membreno Daniel, Smith Leland [link]
"Self-aligned dual-height isolation for bulk FinFET" US PATENT 9564486, Akarvardar Murat Kerem, Bentley Steven John, Cheng Kangguo, Doris Bruce B, Fronheiser Jody, Jacob Ajey Poovannummoottil, Khakifirooz Ali, Nagumo Toshiharu [link]
"Methods for fabricating programmable devices and related structures" US PATENT 9564447, Patil Suraj K, Jacob Ajey P, Chi Minhwa [link]
"Methods of forming different FinFET devices with different threshold voltages and integrated circuit products containing such devices" US PATENT 9564367, Jacob Ajey P, Maszara Witold P, Akarvardar Kerem [link]
2016
"Methods of forming a non-planar ultra-thin body semiconductor device and the resulting devices" US PATENT 9373721, Jacob Ajey Poovannummoottil, Xie Ruilong, Hargrove Michael [link]
"Transistors comprising doped region-gap-doped region structures and methods of fabrication" US PATENT 9368591, Bentley Steven J, Jacob Ajey Poovannummoottil, Chen ChiaYu, Yamashita Tenko [link]
"Methods of forming substrates comprised of different semiconductor materials and the resulting device" US PATENT 9368578, Pawlak Bartlomiej Jan, Bentley Steven, Jacob Ajey [link]
"Channel cladding last process flow for forming a channel region on a FinFET device" US PATENT 9362405, Jacob Ajey Poovannummoottil, Maszara Witold P, Fronheiser Jody A [link]
"FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming" US PATENT 9362277, Chi Minhwa, Jacob Ajey, Paul Abhijeet [link]
"Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device" US PATENT 9349840, Cai Xiuyu, Xie Ruilong, Jacob Ajey P, Maszara Witold P, Cheng Kangguo, Khakifirooz Ali [link]
"Fin transformation process and isolation structures facilitating different Fin isolation schemes" US PATENT 9349730, Jacob Ajey Poovannummoottil, Cheng Kangguo, Doris Bruce B, Loubet Nicolas, Khare Prasanna, Divakaruni Ramachandra [link]
"Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material" US PATENT 9349658, Jacob Ajey Poovannummoottil, Doris Bruce, Cheng Kangguo, Khakifirooz Ali, Rim Kern [link]
"Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region" US PATENT 9343300, Jacob Ajey Poovannummoottil, Hargrove Michael, Fronheiser Jody A, Akarvardar Murat Kerem [link]
"Self-aligned dual-height isolation for bulk FinFET" US PATENT 9324790, Akarvardar Murat Kerem, Bentley Steven John, Cheng Kangguo, Doris Bruce B, Fronheiser Jody, Jacob Ajey Poovannummoottil, Khakifirooz Ali, Nagumo Toshiharu [link]
"Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices" US PATENT 9318552, Xie Ruilong, Taylor, Jr William J, Jacob Ajey Poovannummoottil [link]
"Methods of removing fins for finfet semiconductor devices" US PATENT 9318342, Xie Ruilong, Knorr Andreas, Jacob Ajey Poovannummoottil, Hargrove Michael [link]
"Methods of forming FinFET devices with alternative channel materials" US PATENT 9312387, Jacob Ajey Poovannummoottil, Akarvardar Murat Kerem, Hargrove Michael, Xie Ruilong [link]
"Device isolation in FinFET CMOS" US PATENT 9305846, Jacob Ajey Poovannummoottil, Akarvardar Murat Kerem, Bentley Steven, Nagumo Toshiharu, Cheng Kangguo, Doris Bruce B, Khakifirooz Ali [link]
"Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device" US PATENT 9293587, Jacob Ajey Poovannummoottil, Akarvardar Murat K [link]
"Methods of forming semiconductor devices including an electrically-decoupled fin" US PATENT 9293324, Bentley Steven, Jacob Ajey P [link]
"Method for single fin cuts using selective ion implants" US PATENT 9287130, Cai Xiuyu, Jacob Ajey Poovannummoottil, Xie Ruilong, Doris Bruce, Cheng Kangguo, Cantone Jason R, Mignot Sylvie, Moreau David, Sankarapandian Muthumanickam, Morin Pierre, Fan Su Chen, Choi Kisik, Akarvardar Murat K [link]
"Methods of removing portions of at least one fin structure so as to form isolation regions when forming FinFET semiconductor devices" US PATENT 9269628, Jacob Ajey Poovannummoottil [link]
"Fin device with blocking layer in channel region" US PATENT 9263587, Jacob Ajey P, Chi MinHwa [link]
"Methods of forming isolated channel regions for a FinFET semiconductor device and the resulting device" US PATENT 9263580, Jacob Ajey Poovannummoottil, Loubet Nicolas [link]
"Uniaxially-strained FD-SOI finFET" US PATENT 9252208, Morin Pierre, Vinet Maud, Grenouillet Laurent, Jacob Ajey Poovannummoottil [link]
"Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a FinFET semiconductor device" US PATENT 9245980, Akarvardar Murat Kerem, Fronheiser Jody A, Jacob Ajey Poovannummoottil [link]
"Solid-state supercapacitor" US PATENT 9245694, Dunn Bruce S, Chui Chi On, Jacob Ajey Poovannummoottil, Membreno Daniel, Smith Leland [link]
"Methods of forming replacement fins for a FinFET semiconductor device by performing a replacement growth process" US PATENT 9240342, Jacob Ajey P, Akarvardar Murat K, Fronheiser Jody, Maszara Witold P [link]
"Methods of forming replacement gate structures and fins on FinFET devices and the resulting devices" US PATENT 9236479, Xie Ruilong, Jacob Ajey Poovannummoottil [link]
"Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices" US PATENT 9236258, Xie Ruilong, Cai Xiuyu, Wei Andy C, Zhang Qi, Jacob Ajey Poovannummoottil, Hargrove Michael [link]
2015
"FinFET with insulator under channel" US PATENT 9224865, Akarvardar Murat Kerem, Fronheiser Jody A, Jacob Ajey Poovannummoottil [link]
"Forming alternative material fins with reduced defect density by performing an implantation/anneal defect generation process" US PATENT 9224605, Qi Yi, Jacob Ajey Poovannummoottil, Liang Shurong [link]
"Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device" US PATENT 9214553, Cai Xiuyu, Xie Ruilong, Jacob Ajey P, Maszara Witold P, Cheng Kangguo, Khakifirooz Ali [link]
"Retrograde doped layer for device isolation" US PATENT 9190411, Jacob Ajey Poovannummoottil, Bentley Steven John, Akarvardar Murat Kerem, Fronheiser Jody Alan, Cheng Kangguo, Doris Bruce B, Khakifirooz Ali, Nagumo Toshiharu [link]
"Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices" US PATENT 9184263, Cai Xiuyu, Jacob Ajey Poovannummoottil, Pham Daniel T, Raymond Mark V, Prindle Christopher M, Labelle Catherine B, Jang Linus, Teagle Robert [link]
"FinFET integrated circuits and methods for their fabrication" US PATENT 9184162, Akarvardar Murat Kerem, Cai Xiuyu, Jacob Ajey Poovannummoottil [link]
"Method to form defect free replacement fins by H2 anneal" US PATENT 9165837, Fronheiser Jody, Akarvardar Murat Kerem, Jacob Ajey P, Bentley Steven [link]
"Methods of forming replacement spacer structures on semiconductor devices" US PATENT 9147748, Xie Ruilong, Cai Xiuyu, Jacob Ajey Poovannummoottil, Knorr Andreas, Prindle Christopher [link]
"Methods of forming fins for FinFET semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process" US PATENT 9147730, Xie Ruilong, Knorr Andreas, Jacob Ajey Poovannummoottil, Hargrove Michael [link]
"Methods of forming isolated fins for a FinFET semiconductor device with alternative channel materials" US PATENT 9147616, Jacob Ajey Poovannummoottil, Akarvardar Murat Kerem [link]
"Methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device" US PATENT 9123627, Qi Yi, Jacob Ajey Poovannummoottil, Liang Shurong [link]
"Methods of forming isolated germanium-containing fins for a FinFET semiconductor device" US PATENT 9117875, Jacob Ajey Poovannummoottil, Akarvardar Murat Kerem, Fronheiser Jody A, Cheng Kangguo, Doris Bruce, Rim Kern [link]
"Process for faciltiating fin isolation schemes" US PATENT 9093496, Jacob Ajey P, Cheng Kangguo, Doris Bruce B, Loubet Nicolas, Khare Prasanna, Divakaruni Ramachandra [link]
"Fin pitch scaling and active layer isolation" US PATENT 9076842, Jacob Ajey Poovannummoottil, Akarvardar Murat Kerem, Bentley Steven John, Pawlak Bartlomiej Jan [link]
"Methods of forming replacement gate structures and fins on FinFET devices and the resulting devices" US PATENT 9059042, Xie Ruilong, Jacob Ajey Poovannummoottil [link]
"Methods of forming stressed multilayer FinFET devices with alternative channel materials" US PATENT 9023705, Paul Abhijeet, Jacob Ajey Poovannummoottil, Chi Minhwa [link]
"Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs" US PATENT 9006077, Akarvardar Murat Kerem, Jacob Ajey Poovannummoottil [link]
"FinFET integrated circuits and methods for their fabrication" US PATENT 8987094, Akarvardar Murat Kerem, Cai Xiuyu, Jacob Ajey Poovannummoottil [link]
"Device isolation in finFET CMOS" US PATENT 8963259, Jacob Ajey P, Akarvardar Murat K, Bentley Steven J, Nagumo Toshiharu, Cheng Kangguo, Doris Bruce B, Khakifirooz Ali [link]
2014
"Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process" US PATENT 8853019, Fronheiser Jody A, Wahl Jeremy A, Akarvardar Kerem, Jacob Ajey P, Pham Daniel T [link]
"Integrated circuits and methods for fabricating integrated circuits with cladded non-planar transistor structures" US PATENT 8809947, Akarvardar Kerem Murat, Jacob Ajey Poovannummoottil [link]
"Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process" US PATENT 8716156, Pawlak Bartlomiej Jan, Bentley Steven, Jacob Ajey [link]
"Methods of forming spin torque devices and structures formed thereby" US PATENT 8697454, Nikonov Dmitri E, Bourianoff George I, Jacob Ajey P [link]
"Methods of forming FinFET devices with alternative channel materials" US PATENT 8673718, Maszara Witold P, Jacob Ajey P, LiCausi Nicholas V, Fronheiser Jody A, Akarvardar Kerem [link]
2013
"Methods of forming FinFET devices with alternative channel materials" US PATENT 8580642, Maszara Witold P, Jacob Ajey P, LiCausi Nicholas V, Fronheiser Jody A, Akarvardar Kerem [link]
"Methods of forming spin torque devices and structures formed thereby" US PATENT 8450818, Nikonov Dmitri E, Bourianoff George I, Jacob Ajey P [link]