BibBase crago, s
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  2019 (2)
Increased Fault-Tolerance and Real-Time Performance Resiliency for Stream Processing Workloads through Redundancy. Tran, G. P.; Walters, J. P.; and Crago, S. P. In 2019 IEEE International Conference on Services Computing (SCC), pages 51–55, 2019. IEEE
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Computational requirements for real-time ptychographic image reconstruction. Datta, K.; Rittenbach, A.; Kang, D.; Walters, J. P.; Crago, S. P; and Damoulakis, J. Applied Optics, 58(7): B19–B27. 2019.
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  2018 (3)
Reducing Tail Latencies While Improving Resiliency to Timing Errors for Stream Processing Workloads. Tran, G. P.; Walters, J. P.; and Crago, S. P. In 2018 IEEE/ACM 11th International Conference on Utility and Cloud Computing (UCC), pages 194–203, 2018. IEEE
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Pacer: Automated Feedback-Based Vertical Elasticity for Heterogeneous Soft Real-Time Workloads. Chen, Y.; Tran, G.; Rittenbach, A.; Walters, J.; and Crago, S. P. In 2018 IEEE/ACM 11th International Conference on Utility and Cloud Computing (UCC), pages 73–82, 2018. IEEE
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Reducing Tail Latencies While Improving Resiliency to Timing Errors for Stream Processing Workloads. Tran, G. P.; Walters, J. P.; and Crago, S. P. In 2018 IEEE International Conference on Services Computing (SCC), 2018.
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  2017 (3)
A Comparison of System Performance on a Private OpenStack Cloud and Amazon EC2. Kang, M.; Kang, D.; Walters, J. P.; and Crago, S. P. In 10th IEEE International Conference on Cloud Computing (IEEE Cloud), 2017.
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Dynamically Improving Resiliency to Timing Errors for Stream Processing Workloads. Tran, G. P.; Walters, J. P.; and Crago, S. P. In The 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'17), 2017.
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Load Balancing for Minimizing Deadline Misses and Total Runtime for Connected Car System in Fog Computing. Chen, Y.; Walters, J. P.; and Crago, S. P. In 15th International Symposium on Parallel and Distributed Processing with Applications (ISPA 2017), 2017.
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  2016 (4)
Reducing Data Movement with Approximate Computing Techniques. Crago, S. P.; and Yeung, D. In IEEE International Conference on Rebooting Computing, 2016.
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Hypervisor Performance Analysis for Real-Time Workloads. Tran, G. P.; Chen, Y.; Kang, D.; and Crago, S. P. 2016.
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Automated Demand-Based Vertical Elasticity for Heterogeneous Real-Time Workloads. Tran, G. P.; Chen, Y.; Kang, D.; Walters, J.; and Crago, S. P. 2016.
Automated Demand-Based Vertical Elasticity for Heterogeneous Real-Time Workloads [pdf]Paper   doi   link   bibtex  
The Maestro Flight Experiment: A 49-core radiation hardened processor in space. Rogers, C. M.; Barnhart, D.; and Crago, S. P. 2016.
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  2015 (1)
Supporting High Performance Molecular Dynamics in Virtualized Clusters using IOMMU, SR-IOV, and GPUDirect. Younge, A. J; Walters, J. P.; Crago, S. P; and Fox, G. C In ACM SIGPLAN Notices, volume 50, pages 31–38, 2015. ACM
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  2014 (6)
Dynamic Runtime Optimizations for Systems of Heterogeneous Architectures. Tran, G. P.; Kang, D.; and Crago, S. P. 2014.
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Energy Performance of FPGAs on PERFECT Suite Kernels. Kuppannagari, S.; Chen, R.; Sanny, A.; Singapura, S. G.; Tran, G. P.; Zhou, S.; Hu, Y.; Crago, S. P.; and Prasanna, V. 2014.
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GPU Passthrough Performance: A Comparison of KVM, Xen, VMWare ESXi, and LXC for CUDA and OpenCL Applications. Walters, J. P.; Younge, A.; Kang, D.; Yao, K.; Kang, M.; Crago, S.; and Fox, G. June 2014.
GPU Passthrough Performance: A Comparison of KVM, Xen, VMWare ESXi, and LXC for CUDA and OpenCL Applications [pdf]Paper   doi   link   bibtex  
Bridging the Virtualization Performance Gap for HPC Using SR-IOV for InfiniBand. Musleh, M.; Pai, V. S.; Walters, J. P.; Younge, A.; and Crago, S. P. 2014.
Bridging the Virtualization Performance Gap for HPC Using SR-IOV for InfiniBand [pdf]Paper   link   bibtex  
Maestro Software and Application Performance. Walters, J. P.; Rogers, C. M.; and Crago, S. P. 2014.
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Evaluating GPU Passthrough in Xen for High Performance Cloud Computing. Younge, A. J.; Walters, J. P.; Crago, S. P.; and Fox, G. C. 2014.
Evaluating GPU Passthrough in Xen for High Performance Cloud Computing [pdf]Paper   link   bibtex  
  2013 (1)
Implementation of Kernels on the Maestro Processor. Suh, J.; Kang, D.; and Crago, S. P. In IEEE Aerospace Conference, pages 1-6, March 2013.
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  2012 (2)
Integrating High Performance File Systems in a Cloud Computing Environment. Pan, A.; Walters, J. P.; Pai, V. S.; Kang, D.; and Crago, S. P. In International Workshop on Data-Intensive Scalable Computing Systems, held in conjunction with SC12, November 2012.
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Implementation of FFT and CRBLASTER on the Maestro Processor. Suh, J.; Mighell, K. J.; Kang, D.; and Crago, S. P. In IEEE Aerospace Conference, pages 1-6, March 2012.
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  2011 (5)
Heterogeneous Cloud Computing. Crago, S.; Dunn, K.; Eads, P.; Hochstein, L.; Kang, D.; Kang, M.; Modium, D.; Singh, K.; Suh, J.; and Walters, J. P. In Workshop on Parallel Programming on Accelerator Clusters (PPAC2011), September 2011.
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Programming Models and Development Software for a Space-Based Many-Core Processor. Crago, S. P.; Kang, D.; Kost, R.; Singh, K.; Suh, J.; and Walters, J. P. In Fourth IEEE International Conference on Space Mission Challenges for Information Technology, August 2011.
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Multi-Core Fault Tolerance for Space. Crago, S. P.; Walters, J. P.; Kost, R.; Singh, K.; and Suh, J. In GOMACTech, March 2011.
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Software-Based Fault Tolerance for the Maestro Many-Core Processor. Walters, J. P.; Kost, R.; Singh, K.; Suh, J.; and Crago, S. P. In IEEE Aerospace Conference, March 2011.
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FFTW and Complex Ambiguity Function Performance on the Maestro Processor. Singh, K.; Walters, J. P.; Hestness, J.; Suh, J.; Rogers, C. M.; and Crago, S. P. In IEEE Aerospace Conference, March 2011.
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  2010 (1)
Opportunities for concurrent dynamics analysis with explicit inter-core communication. Ha, J.; and Crago, S. P. In ACM SIGPLAN-SIGSOFT Workshop on Program Analysis for Software Tools and Engineering (PASTE), June 2010.
Opportunities for concurrent dynamics analysis with explicit inter-core communication [link]Paper   doi   link   bibtex  
  2009 (3)
Mission-Critical Space Software for Multi-Core Processors. Crago, S. P. In Workshop on Flight Software, November 2009.
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Maestro Multi-Core Software. Crago, S. P. In Workshop on Multi-Core Processors for Space- Opportunities and Challenges held in conjunction with Third IEEE International Conference on Space Mission Challenges for Information Technology, July 2009.
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Integrated Development Environment and Parallel Performance Analysis Tools for Tile 64/ Maestro. Singh, K.; Kost, R.; Yoo, K.; Parker, K.; and Crago, S. P. In Workshop on Multi-Core Processors for Space- Opportunities and Challenges held in conjunction with IEEE SMC-IT, July 2009.
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  2008 (1)
Advanaced Microprocessor Architectures. McMahon, J. O.; Crago, S. P.; and Yeung, D. In High Performance Embedded Computing Hanbook. CRC Press, 2008.
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  2007 (2)
Preliminary Study toward Intelligent Run-time Resource Management Techniques for Large Multi-Core Architectures. Kang, D.; Suh, J.; McMahon, J. O.; and Crago, S. P. In High Performance Embedded Computing (HPEC), September 2007.
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Optimization of Memory Allocation in VSIPL. Suh, J.; McMahon, J. O.; Kang, D.; and Crago, S. P. In High Performance Embedded Computing (HPEC), Poster Session, September 2007.
Optimization of Memory Allocation in VSIPL [pdf]Paper   link   bibtex  
  2006 (2)
Design and Evaluation of Hierarchical Decoupled Architecture. Ro, W. W.; Crago, S. P.; Despain, A. M.; and Gaudiot, J. The Journal of Supercomputing, 38(3): 237-259. December 2006.
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CEARCH: Cognition Enabled Architecture. Crago, S. P.; McMahon, J. O.; Archer, C.; Asanovic, K.; Chaung, R.; Goolsbey, K.; Hall, M.; Kozyrakis, C.; Olukotun, K.; 0'Reilly, U.; Pancoast, R.; Prasanna, V.; Rabbah, R.; Ward, S.; and Yeung, D. In Proceedings of the Tenth Annual High Performance Embedded Computing Workshop, September 2006.
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  2005 (3)
Implementations of Signal Processing Kernel using Stream Virtual Machine for Raw Processors. Suh, J.; Crago, S. P.; Kang, D.; and McMahon, J. O. In High Performance Embedded Computing (HPEC), September 2005.
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Implementation of an Embedded DoD VSIPL Application on the SARPA Polymorphous Computing Architecture (PCA) Raw Processor. Cook, J.; Crago, S. P.; Morda, L.; Pancoast, R.; and Suh, J. In High Performance Embedded Computing (HPEC), September 2005.
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Multiprocessor Performance for Polymorphous Computing Systems. Crago, S. P.; French, M. C.; Suh, J.; Chen, C.; and Campbell, D. P. In Government Microcircuit Applications and Critical Technology Conference (GOMAC), April 2005.
Multiprocessor Performance for Polymorphous Computing Systems [link]Paper   link   bibtex  
  2004 (1)
Novel Signal Processing Architectures for Knowledge-based STAP Algorithms. French, M. C.; Suh, J.; Crago, S. P.; and John, D. In IEEE Radar Conference, April 2004.
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  2003 (5)
Dynamic Power Management of Heterogeneous Systems. Suh, J.; Kang, D.; and Crago, S. In Eleventh International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS) in conjunction with IPDPS, April 2003.
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Robust Highly-Connected Direct Interconnection Network Topologies. Sharapov, I.; Lauterbach, G.; and Crago, S. In International Conference on Parallel and Distributed Processing Techniques and Applications, June 2003.
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A Performance Characterization of New Microprocessor paradigm on Data-Intensive Kernels. Suh, J.; Kim, E.; Crago, S. P.; Srinivasan, L.; and French, M. C. In Workshop on Performance Characterization, Modeling, and Benchmarking for HPC Systems, May 2003.
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HiDISC: a decoupled architecture for data-intensive applications. Ro, W.; Gaudiot, J.; Crago, S. P.; and Despain, A. M. In International Parallel and Distributed Processing Symposium, April 2003.
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System Architecture Issues for Polymorphous Computing. Crago, S. P.; Suh, J.; Chen, C.; Kang, D.; and Kim, E. In 28th Annual GOMACTech Conference, April 2003.
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  2002 (5)
A Power-Aware, Satellite-Based Parallel Signal Processing Scheme. Shriver, P. M.; Gokhale, M. B.; Briles, S. D.; Kang, D.; Cai, M.; McCabe, K.; Crago, S. P; and Suh, J. In Power Aware Computing, Series in Computer Science, Kluwer Academic/Plenum Publishers, 2002.
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VLSI in Computers and Processors. Serebrin, B.; Owens, J. D.; Chen, C. H.; Crago, S. P.; Kapasi, U. J.; Khailany, B.; Mattson, P.; Namkoong, J.; Rixner, S.; and Dally, W. J. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, September 2002.
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DARPA Data Intensive Systems (DIS) Embedded Computing Benchmarks for Critical Defense Signal Processing Applications. Shank, S. F.; Crago, S.; Pancoast, R.; Racosky, J.; Suh, J.; and Trevito, L. In 6th Annual High Performance Embedded Computing Workshop, September 2002.
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An Optimal Voltage Synthesis Technique for a Power-Efficient Satellite Application. Kang, D.; Suh, J.; and Crago, S. In 39th Design Automation Conference (DAC), pages 492–497, June 2002.
An Optimal Voltage Synthesis Technique for a Power-Efficient Satellite Application [link]Paper   doi   link   bibtex  
Dynamic Power Management of Multiprocessor Systems. Suh, J.; Kang, D.; and Crago, S. In Tenth International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS) in conjunction with IPDPS, April 2002.
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  2001 (6)
PIM- and Stream Processor-based Processing for Radar Signal Applications. Suh, J.; and Crago, S. P In The Third Workshop on Media and Streaming Processors in conjunction with The 34th International Symposium on Microarchitecture, December 2001.
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PIM- and Stream Processor-Based System. Suh, J.; Crago, S. P; Li, C.; and Parker, R. In Fifth Annual High Performance Embedded Computing Workshop, November 2001.
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Efficient Algorithms for Fixed-Point Arithmetic Operations In An Embedded PIM. Suh, J.; Kang, D.; and Crago, S. P In SCI 01, July 2001.
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Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems. Kang, D.; Crago, S. P; and Suh, J. In ACM Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES) '01, June 2001.
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A PIM-Based Multiprocessor. Suh, J.; Li, C.; Crago, S. P; and Parker, R. In IPDPS 01, April 2001.
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Implementations of Real-time Data Intensive Applications on PIM-based Multiprocessor Systems. Suh, J.; Zhu, M.; Li, C.; Crago, S. P; Shank, S. F.; Chau, R. H.; Mazur, W. J.; and Pancoast, R. In Joint WPDRTS and EHPC 01, April 2001.
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  2000 (3)
A High-Performance, Hierarchical Decoupled Architecture. Crago, S. P.; Despain, A. M.; Gaudiot, J.; Makhija, M.; Ro, W.; and Srivastava, A. In MEmory access DEcoupling for superscalar and multiple issue Architectures (MEDEA) Workshop, October 2000.
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Distributed Corner Turn on a PIM-Based Multiprocessor. Suh, J.; Crago, S. P; Li, C.; and Parker, R. In Fourth Annual Workshop on High Performance Embedded Computing (HPEC), September 2000.
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A Communication Scheduling Algorithm for Multi-FPGA Systems. Suh, J.; Kang, D.; and Crago, S. P In IEEE Symposium on Field Programmable Custom Computing Machines (FCCM) 2000, April 2000.
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  1998 (2)
A Hierarchical Decoupled Instruction Stream Architecture. Crago, S. P. Ph.D. Thesis, University of Southern California, May 1998.
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SLAAC: A Distributed Architecture for Adaptive Computing. Crago, S. P.; Schott, B.; and Parker, R. In IEEE Symposium on FPGAs for Custom Computing Machines, April 1998.
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  1997 (1)
HiDISC: A Decoupled Architecture for the Future. Crago, S. P.; and Despain, A. M. In ACAL-TR-97-01, January 1997.
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  1996 (3)
Reducing the Traffic of Loop-Based Programs Using a Prefetch Processor. Crago, S. P.; and Despain, A. M. In ACAL-TR-96-08, December 1996.
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Improving the Performance of Loop-Based Programs Using a Prefetch Processor. Crago, S. P.; and Despain, A. M. In ACAL-TR-96-07, November 1996.
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A High-Performance, Hierarchical Decoupled Architecture. Crago, S. P.; Srivastava, A.; Obenland, K.; and Despain, A. M. In ACAL-TR-96-02, June 1996.
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  1992 (1)
Use of Synthetic Traces to Analyze Cache Performance. Crago, S. P. masters, Purdue University, May 1992.
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  1990 (1)
Automatic Splitting of IF-THEN-ELSE Statements. Crago, S. P. In IBM Technical Disclosure Bullentin, December 1990.
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  undefined (1)
A Performance Analysis of PIM, Stream Processing and Tiled Processing on Memory-Intensive Signal Processing Kernels. In ISCA03, pages 410–421, .
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