Historical Projects
Completed Projects
- BitBandit
- COMBAT: Cooperative Multicast and Broadcast at the Tactical Edge
- EMBARK: Evaluation of Mapping NLP based Algorithms into Reconfigurable Computing Kernels
- HAVoC: Hardened Adversarial Challenge
- Redsharc: Reconfigurable Data Stream Hardware/Software Architecture
- RHinO: Reconfigurable Hardware in Orbit
- SCX: SpaceCubeX
- SPICY: Hot & Spicy: Improving Productivity with Python and HLS for FPGAs
- TORC: Tools for Open Reconfigurable Computing
- SAPIENT: Scalable Acceleration Platform Integrating Reconfigurable Computing and Natural Language Processing Technologies
BitBandit
BitBandit is a self-contained SoC fault injector for a processor's general/special purpose registers and instruction/data caches for FPGA devices. Faults are injected through a combination of hardware and software running within the processor and FPGA fabric. BitBandit supports scalable fault injection campaigns to emulate malicious and/or environmental corruptions. The initial release of BitBandit open-source infrastructure supports Xilinx Virtex4 FX devices with an integrated PowerPC 405 processor.
COMBAT: Cooperative Multicast and Broadcast at the Tactical Edge
Enabling next generation low latency protocols in software defined radios.
EMBARK: Evaluation of Mapping NLP based Algorithms into Reconfigurable Computing Kernels
With advancements in high-speed interfaces, integrated DSP hard IP, and on-chip memory densities, FPGAs can leverage pipe-lining and parallelism to compensate for limitations like slower clock rates etc
HAVoC: Hardened Adversarial Challenge
Adversarial challenge development for the DARPA VET program for FPGAs.
Redsharc: Reconfigurable Data Stream Hardware/Software Architecture
The Reconfigurable Data Stream Hardware/Software Architecture (Redsharc) is a set of IP & API to migrate sequential software to parallel hw/sw MPSoC. Redsharc simplifies control of the system: scheduling/mapping, communication, and data transfer between cores and enables application to scale over different configurations of cores.
RHinO: The Reconfigurable Hardware in Orbit
The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology.
SCX: SpaceCubeX
Heterogeneous on board computing platforms to support next generation Earth science missions.
SPICY: Hot & Spicy: Improving Productivity with Python and HLS for FPGAs
Hot & Spicy is an open-source infrastructure and tool suite for integrating FPGA accelerators in Python applications, provided entirely as Python source code. This suite of tools eases the packaging, integration, and binding of accelerators and their C/C++ based drivers callable from a Python application. The tools can:
- Translate Python functions to HLS-suitable C functions
- Generate Python C wrapper bindings
- Automate the FPGA EDA tool flow
- Retarget Python source code to use accelerated libraries
For FPGA experts, this enables increased productivity and supports research on each stage of the flow by providing a framework to integrate additional compilers and optimizations. For everyone else this enables fast, consistent, acceleration of applications on FPGAs.
TORC: Tools for Open Reconfigurable Computing
Torc is an open-source C++ infrastructure and tool set for reconfigurable computing. It is suitable for custom research applications, for CAD tool development, for architecture exploration, and for any application that needs to work with real-world physical device data. Torc can serve as the basis for research in synthesis, mapping, placing, and routing. It may also prove to be useful in productivity enhancements, power optimization, radiation tolerance, security, and other domains that are sometimes overlooked by the commercial industry.
SAPIENT: Scalable Acceleration Platform Integrating Reconfigurable Computing and Natural Language Processing Technologies
The SAPIENT project encompasses several capabilities to accelerate Natural Language Processing tasks on Field-Programmable Gate Array based High-Performance Computing systems.
