Project Navigation

The Comprehensive Independent Functional Testing tools (CIFT) is researching algorithmic generation of independent functional tests that can be used to cross-check the FPGA manufacturer’s testing and in field testing for counterfeit, damaged, or aging parts.  Functional testing of commercial FPGAs, independent of in-house FPGA vendor production testing, is an important first step in establishing a trusted supply-chain, determining the usability of devices stored in inventory for long periods of time, verifying complex 2.5D and 3D packages, and determining the health status of fielded systems. Independent functional testing of the FPGA VLSI provides an open, transparent check that the device is in fact the device it claims to be and is in good working order. This is no trivial feat as modern FPGA devices now contain over 10B transistors, over a dozen types of Hard IP, 35M user wires, and 380M user routing switches.

CIFT tests include detection of stuck at faults in CLB/LAB/PLB resources, embedded block RAMs, configuration memory, and routing interconnect paths in FPGAs in over 14 device families including devices from AMD/Xilinx, Intel, Microsemi, and Lattice.  CIFT manages the automated creation of test bitstreams, the programming and running of test on hardware, and the extraction and collection of status of the hardware.  Further CIFT work is looking into addressing additional device fault models including measuring the parametric delay throughout a device.

Interconnect Testing

Custom massively replicatable paths to exercise PIPs: one signal exiting to left and another signal arriving from right, passing through PIPs.

Logic Testing

Paths through configurable logic
Flip-flop on right enables launch and capture of test signals through logic

Runtime Optimization

Utilize techniques such as partial runtime reconfiguration to reduce runtime

The material is based on research sponsored by the Navy, Air Force Research Labs (AFRL), and the Defense Advanced Projects Agency (DARPA) under agreement number FA8650-18-1-7817. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the Navy, Air Force Research Labs (AFRL), the Defense Advanced Projects Agency (DARPA), or the U.S. Government. This work is also supported by generous donations from Synopsys and Cadence.

Independent Functional Testing of Commercial FPGA Devices.
M. French, N. Steiner, J. Draper, et al, Government Microcircuit Applications and Critical Technology Conference (GOMACTech), 2016.
Paper | Presentation

Leadership

Research Staff

Subhajit Dutta Chowdry

Research Staff

Neil Steiner

Research Staff

Joshua Monson

Research Staff

Research Assistants

Aidin Shiri
Anuj Patil
Hunain Ali Shamsi
Monica Reddy Pottipati
Shlok Agarwal
Tendayi Kamucheka
Yuanzhe Jin
Devang Khamar
Dhanush Srinivasa
Max Yu
Pantea Kiaei
Shlok Agarwal
Kruthika Ravi
Devang Kumar

Collaborators

Georgia Tech Research Institute (GTRI)

Virginia Tech