M.S., Electrical and Computer Engineering, University of Colorado, Boulder
B.S., Electronic Engineering, Chung-Yuan Christian University, Taiwan ROC
Ting-Yuan received his M.S.E.E from Univerisity of Colorado - Boulder focus on IC CAD design. After graduated from school, he has worked as RD engineers in developing various EDA software systems including logic synthesis, simulation, SOC integration, Place and Route.
Ting-Yuan has worked in Synplicity Inc as Algorithm Developer. The project involved placement synthesis engine used in Altera and Xilinx mapper. In 2016, he also worked in Xilinx as contractor involving in SOC integration flow and tool development.
From 2001 to 2012, he worked in Synopsys Inc in developing fast-spice simulator(HSIM) and power rail analysis tool(RailMill). The main focus are the circuit partition and matrix solver engine. The key is to improve simulation performance, i.e. run time from weeks to hours.
His past experience Intel Inc including developing SOC/IP pre-silicon design verification and EDA tool integration.
In USC/ISI, he also involved in CIFT/Galatica Gopher/Brace projects with RCG group.
CIFT (Comprehensive Independent Functional for FPGA Testing tool) - Focus Spartan6/Spartan7devices for LUT/BRAM/Interconnect testing in post-P&R simulation and bitstreams board testing. With this project, He also involved in test developing with scripting to generating continuity report using spreadsheet to maintain quality control.
Galatic Gopher - Focus on the FPGA logic equivalence checker(LEC) for Vivado Synthesis and Synopsys's Formality integration for Xilinx devices.
Brace (Bitstream Assurance Checking Engine for Undocumented Functionality) - Integration PrjXray/FASM2BEL flow for static bitstream checker for various IPs.