In today’s global marketplace, IP protection is becoming a serious concern in ASIC development. Circuit-level obfuscation is a potentially viable solution, however no common metrics exist to evaluate these techniques and no design tools exist to guide and validate implementation. Mirage utilizes quantitative security and overhead metrics to ascertain which obfuscation techniques provide realistic levels of security and utilizes state of the art design space exploration techniques to select and apply the best techniques for a given circuit.

Mirage is principally composed of a front end Obfuscation Design Space Exploration engine which utilizes feedback from security metrics to drive selection of obfuscation IP and is interoperable with standard ASIC EDA tools. Mirage utilizes Design Space Exploration (DSE) algorithms well suited for large search spaces leveraging intelligent pruning and compositional reasoning. The Security-centric metrics that are applicable to both passive and active obfuscation techniques. Mirage focuses on unified, adversary centric models that are applicable across a range of obfuscation types. In addition to overhead metrics, Mirage also provides techniques for verification of the correct application of the obfuscation.

The material is based on research sponsored by the Air Force Research Labs (AFRL) and the Defense Advanced Projects Agency (DARPA) under agreement number FA8650-18-1-7817. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the Air Force Research Labs (AFRL), the Defense Advanced Projects Agency (DARPA), or the U.S. Government. This work is also supported by generous donations from Synopsys and Cadence.