Abstract

This paper proposes an approximation algorithm for clocking assignments that minimizes the insertion of path balancing DFFs for multi-threaded multi-phase clocking of SFQ circuits. Existing SFQ multi-phase clocking solutions have been shown to effectively reduce the number of required DFFs in-serted, however, the associated clock assignment algorithms have exponential complexity and can have prohibitively long runtimes for large circuits, limiting the scalability of this approach. Our proposed algorithm is based on a linear program (LP) that leads to solutions that are experimentally on average within 5% of the optimum, permitting multi-phase clocking schemes to scale to larger SFQ circuits than previous state of the art clocking assignment methods. We further extend our algorithm to support fanout sharing of the added DFFs, saving, on average, an additional 11 % of the inserted DFFs compared to the state of …

Date

2024

Authors

Robert S Aviles, Xi Li, Lei Lu, Zhaorui Ni, Peter A Beerel

Conference

2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

Pages

266-271

Publisher

IEEE