Abstract

Latches are smaller and lower power than flip-flops (FFs) and are typically used in a time-borrowing master-slave configuration. This paper presents an automatic flow for converting arbitrarily-complex single-clock-domain FF-based RTL designs to efficient 3-phase latch-based designs with reduced number of required latches, saving both register and clock-tree power. Post place-and-route results demonstrate that our 3-phase latch-based designs save an average of 15.5% and 18.5% power on a variety of ISCAS, CEP, and CPU benchmark circuits, compared to their more traditional FF and master-slave based alternatives.

Date

2020

Authors

Huimei Cheng, Xi Li, Yichen Gu, Peter A Beerel

Conference

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Pages

574-579

Publisher

IEEE