Abstract

This paper proposes a family of modular interfaces for crossing between asynchronous and synchronous timing domains. Motivated by asynchronous NoC and desynchronized pipelines, these converters support two-phase, bundled data communication. They provide high-throughput communication and support an early-request protocol that can hide most of the synchronization latency. Our designs are fully synthesizable using widely available standard cell libraries and a standard ASIC design flow. The converters have been integrated into an opensource bundled-data desynchronization flow and evaluated in isolation as well in the context of an encryption engine supporting three block ciphers.

Date

2019

Authors

Ameer Abdelhadi, Dake Chen, Huimei Cheng, Gourav Datta, Yang Zhang, Peter Beerel, Mark Greenstreet

Journal

25th IEEE International Symposium on Asynchronous Circuits and Systems-Fresh Ideas