Abstract

A novel diversely body‐biased current‐starved delay element (DE) architecture for fine‐grained DEs is presented. Using fully depleted silicon‐on‐insulator back‐body biasing, it achieves a resolution of 2 ps with a delay quantisation error of 7.1%. Compared with the state‐of‐the‐art DEs, it exhibits the least leakage current and efficient overall energy consumption and is the most robust to process variations.

Date

2015

Authors

W Hua, RN Tadros, P Beerel

Journal

Electronics Letters

Volume

51

Issue

23

Pages

1848-1850

Publisher

The Institution of Engineering and Technology