Abstract

Contemporary digitally controlled delay elements trade off power overheads and delay quantization error. This paper proposes a new delay element that provides a balanced design that yields low power with low delay quantization error. The proposed element has a quasi linear delay characteristic, with uniform delay differences between adjacent code words. The element employs and leverages the advantages offered by a 28nm FD-SOI technology, using its back body biasing feature to add an extra dimension to its programmability. To do so, a novel generic delay shift block is proposed, which enables incorporating both fine and coarse delays in a single delay element that can be easily integrated into digital systems, an advantage over hybrid delay elements that rely on analog design.

Date

2015

Authors

Ajay Singhvi, Matheus T Moreira, Ramy N Tadros, Ney LV Calazans, Peter A Beerel

Conference

2015 IEEE Computer Society Annual Symposium on VLSI

Pages

27-32

Publisher

IEEE