Abstract

We describe a method in which resynthesis is applied to the bundled-data implementation of a production-level Intel architecture CPU (Quark) to improve performance and area. A two-step quadratic program is presented for optimally adjusting the new flop-to-flop path constraints for resynthesis. Our experimental results show an average improvement of 25% in performance at the same area cost.

Date

2014

Authors

Arash Saifhashemi, Dylan Hand, Peter A Beerel, William Koven, Hong Wang

Conference

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems

Pages

110-111

Publisher

IEEE