Abstract

The design of a commercially-shipping 72-port 10G Ethernet switch router integrated circuit is presented. The 1.2 billion transistor chip consists of a core of > 1GHz asynchronous circuits surrounded by standard synchronous logic for external interfaces. It is manufactured in a TSMC 65nm process. The asynchronous circuitry includes 15MB of single-ported SRAM, 150KB of dual-ported SRAM, 100KB of TCAM, Tb bandwidth crossbars, and a fully pipelined programmable packet processor processing one billion packets per second. The design implementation relied heavily on a novel tool flow utilizing both commercial and proprietary EDA tools for automatic place-and-route of asynchronous layout.

Date

2014

Authors

Mike Davies, Andrew Lines, Jon Dama, Alain Gravel, Robert Southworth, Georgios Dimou, Peter Beerel

Conference

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems

Pages

103-104

Publisher

IEEE