Abstract

This paper proposes the method of generating asynchronous circuits from hardware description language specifications by clustering the synthesized gates into asynchronous pipeline stages while preserving liveness, meeting throughput and latency constraints, and minimizing area. This method provides a form of automatic pipelining in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original Register-Transfer Level (RTL) specification. The method is design-style agnostic and is thus applicable to many asynchronous design styles.

Date

2014

Authors

Georgios D Dimou, Peter A Beerel, Andrew M Lines

Journal

IEEE Transactions on computer-aided design of integrated circuits and systems

Volume

33

Issue

2

Pages

197-209

Publisher

IEEE