Abstract

Introduction and Motivation Introduction and Motivation The Solution – An SDC Language Enhancements and Pre-processor The Solu Page 1 Enhanced SDC Support for Relative Timing Designs Introduction and Motivation University of Southern California Eric Quist ([email protected]) Peter Beerel ([email protected]) University of Utah Kenneth Stevens ([email protected]) Introduction and Motivation The context – Asynchronous Circuits • Synchronous designs are faced with increasing complexity • Problems include clock tree synthesis, hold time fixing, clock skew management and increasing power consumption • Asynchronous designs offer several advantages • Low power consumption • Low latency and high throughput Sample Relative Timing Circuit Motivation • Current state of the art • Constraints such as set_max_delay, set_mid_delay, set_data_check, and set_disable_timing allow for relative timing …

Date

2009

Authors

Eric Quist, Peter Beerel, KS Stevens

Journal

Digital Automation Conference, User Track Poster