Abstract

This paper presents the design of a channel-based asynchronous sequential decoder implemented with quasi-delay-insensitive templates. The Powermill simulation results in TSMC 0.25-CMOS technology show that the circuit runs at 430 MHz and consumes 32 mW. Techniques to effectively partition and implement the top level design, the implementation of fast shift registers, memories, and various other structures are discussed. Compared to a previously designed synchronous Fano decoder, the asynchronous version consumes 1/3 the power and runs at 2.15 times the speed assuming standard process normalization. The design also highlights the introduction of a standard-cell library and back-end design flow for asynchronous designs based on precharged half buffer (PCHB) templates

Date

2006

Authors

Recep O Ozdag, Peter A Beerel

Journal

IEEE transactions on very large scale integration (VLSI) systems

Volume

14

Issue

9

Pages

975-985

Publisher

IEEE