Abstract

This paper presents the development of a prototype high-performance asynchronous standard-cell library based on the static single-track full buffer family. It focuses on the design choices and challenges that mitigate sensitiveness to noise, including transistor sizing and wire spacing rules. Post-layout simulation results demonstrate its robustness to noise while achieving a peak cycle time of 5.7 FO4 delays

Date

2006

Authors

Pankaj Golani, Peter A Beerel

Conference

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

Pages

6 pp.

Publisher

IEEE