Abstract

Asynchronous design is emerging as a practical alternative to synchronous design for both low power and high performance applications. Moreover, ASIC flows that support asynchronous design are becoming complete, including many that leverage existing front-end and back-end synchronous-oriented tools. This talk will review the different design styles and flows and highlight some of the on-going commercialization efforts in this area. Special attention will be paid to the single-track circuit families developed at USC that provide ultra high performance and low power characteristics. We will review the associated standard-cell libraries and flows that have been developed as well as the recent chip design efforts that demonstrate the benefits of this technology.

Date

2006

Authors

Peter A Beerel

Book

International Workshop on Power and Timing Modeling, Optimization and Simulation

Pages

669-669

Publisher

Springer Berlin Heidelberg