Abstract

In this paper we describe a method for modeling channel-based asynchronous circuits using Verilog HDL. We suggest a method to model CSP-like channels in Verilog HDL. This method also describes nonlinear pipelines and highlevel channel timing properties, such as forward and backward latencies, minimum cycle time, and slack. Using Verilog enables us to describe the circuit at many levels of abstraction and to use the commercially available CAD tools.

Date

2005

Authors

Jan Broenink, Herman Roebbers, Johan Sunter, Peter Welch, David Wood

Journal

Communicating Process Architectures

Pages

275