Abstract

This work presents the design of a channel-based asynchronous sequential decoder implemented with quasi-delay-insensitive templates. The Powermill/spl copy/ simulation results in TSMC 0.25 CMOS technology show that the circuit runs at 430MHz and consumes 32mW. Techniques to effectively partition and implement the top-level design, the implementation of fast shift registers, memories, and various other structures are discussed. Compared to a previously designed synchronous Fano decoder, the asynchronous version consumes 1/3 the power and runs at 2.15 times the speed assuming standard process normalization. The design also highlights the introduction of a standard-cell library and back-end design flow for asynchronous designs based on PCHB templates.

Date

2004

Authors

Recep O Ozdag, Peter A Beerel

Conference

10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.

Pages

187-197

Publisher

IEEE