Publications

Accurate and Efficient CMP Process Modeling for Design for Manufacturability at Advanced Logic Processes

Abstract

Prediction 4 outputs: Cu thickness, ILD thickness, ILD height and Surface height Detect 3 hotspots: Step Height, Cu thickness, Surface Height to identify weak points in the design caused by dishing, erosion and pooling effects Find Multi-layer cumulative effects: The Cu thickness and surface topography of the later layer is affected by the previous layer topography CMP Model applications in DFM Service at SMIC: Check the product chips sensitivity to CMP process. So far about 20 tape-outs, 230 40nm gds files have been checked after new model’s release, the final results are closely correlated between the simulation and real Si-data.

Date
2012
Authors
Zhong Fan, Helen Li, Linda Lv, Mealie Zhang, Tyzy Lee, Elain Zou, LiFu Chang