Abstract

The NetFPGA network interface card provides a platform for deploying reconfigurable hardware in the network. Researchers are able to build and simulate a design within an integrated design environment; however debugging a design on the NetFPGA itself is non-trivial. Furthermore, manually creating signals and input data for a simulation that accurately represents a real network data flow is difficult. In this paper we present a NetFPGA Logic Analyzer with a triggering mechanism that captures the control signals and data path of the NetFPGA at the full 125M samples per second for the allotted duration. The triggering mechanism is a programmable pattern matcher module with mask that can be modified while the system is online. The trace data is copied to the host CPU where it is converted into a Verilog test benchmark file. The testbench then can be integrated to the rest of the NetFPGA file simulation for the purpose of precise logic debugging and validation.

Date

2010

Authors

Andrew Goodney, N Shailesh, W Mengchen, S Peigen, B Vivek, Young H Cho

Journal

2nd North American NetFPGA developers workshop